DATA SHEET

COMPOUND FIELD EFFECT POWER TRANSISTOR

µ PA1560
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE

DESCRIPTION PACKAGE DRAWING (Unit : mm)

The µPA1560 is N-Channel Power MOS FET Array 26.8 MAX. 4.0
that built in 4 circuits designed for solenoid, motor and

10
lamp driver.

10 MIN.
2.5
FEATURES
• Full mold package with 4 circuits 1.4
2.54
• 4 V driving is possible 1.4 0.6±0.1 0.5±0.1

• Low on-state resistance

RDS(on)1 = 165 mΩ MAX. (VGS = 10 V, ID = 1.5 A)
1 2 3 4 5 6 7 8 910
RDS(on)2 = 200 mΩ MAX. (VGS = 4 V, ID = 1.5 A)
• Low input capacitance EQUIVALENT CIRCUIT
Ciss = 600 pF TYP.
3 5 7 9
ORDERING INFORMATION
PART NUMBER PACKAGE 2 4 6 8

1 10
µ PA1560H 10-pin SIP
ELECTRODE CONNECTION
2, 4, 6, 8 : Gate
3, 5, 7, 9 : Drain
1, 10 : Source

ABSOLUTE MAXIMUM RATINGS (TA = 25°C)

Drain to Source Voltage (VGS = 0 V) VDSS 120 V
Gate to Source Voltage (VDS = 0 V) VGSS(AC) ±20 V
Gate to Source Voltage (VDS = 0 V) VGSS(DC) + 20, –10 V
Drain Current (DC) ID(DC) ±3.0 A
Note1
Drain Current (pulse) ID(pulse) ±12 A
Total Power Dissipation (TC = 25°C) PT1 28 W
Total Power Dissipation (TA = 25°C) PT2 3.7 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg –55 to + 150 °C
Note2
Single Avalanche Current IAS 3.0 A
Note2
Single Avalanche Energy EAS 0.9 mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %
2. Starting Tch = 25 °C, VDD = 60 V, RG = 25 Ω, VGS = 20 V → 0 V

Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. G14283EJ1V0DS00 (1st edition)

Date Published April 1999 NS CP(K)
Printed in Japan
© 1999
 µ PA1560

ELECTRICAL CHARACTERISTICS (TA = 25 °C)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Drain to Source On-state Resistance RDS(on)1 VGS = 10 V, ID = 1.5 A 130 165 mΩ

RDS(on)2 VGS = 4.0 V, ID = 1.5 A 145 200 mΩ

Gate to Source Cut-off Voltage VGS(off) VDS = 10 V, ID = 1.0 mA 1.0 1.8 2.5 V

Forward Transfer Admittance | yfs | VDS = 10 V, ID = 1.5 A 2 4.5 S

Drain Leakage Current IDSS VDS = 120 V, VGS = 0 V 10 µA

Gate to Source Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA

Input Capacitance Ciss VDS = 10 V 600 pF

Output Capacitance Coss VGS = 0 V 160 pF

Reverse Transfer Capacitance Crss f = 1.0 MHz 70 pF

Turn-on Delay Time t d(on) ID = 1.5 A 35 ns

Rise Time tr VGS(on) = 10 V 80 ns

Turn-off Delay Time td(off) VDD = 60 V 700 ns

Fall Time tf RL = 30 Ω 250 ns

Total Gate Charge QG ID = 3.0 A 28 nC

Gate to Source Charge QGS VDD = 96 V 2.5 nC

Gate to Drain Charge QGD VGS = 10 V 9 nC

Body Diode Forward Voltage VF(S-D) IF = 3.0 A, VGS = 0 V 0.9 V

Reverse Recovery Time trr IF = 3.0 A, VGS = 0 V 160 ns

Reverse Recovery Charge Qrr di/dt = 50 A/ µs 280 nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T. D.U.T.
RG = 25 Ω L
RL VGS
VGS 90 %
10 % VGS(on)
PG Wave Form
0
50 Ω VDD RG
PG. RG = 10 Ω VDD
VGS = 20 → 0 V
ID 90 %
90 %
ID
BVDSS VGS 10 %
IAS ID 0 10 %
0 Wave Form
VDS
ID τ td(on) tr td(off) tf
VDD
ton toff
τ = 1µ s
Duty Cycle ≤ 1 %
Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.
IG = 2 mA RL

PG. 50 Ω VDD

2 Data Sheet G14283EJ1V0DS00

 µ PA1560

[MEMO]

Data Sheet G14283EJ1V0DS00 3

 µ PA1560

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M7 98. 8