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131 Literature Survey Report

This paper proposes a new robust non-overlapping two-phase clock generator circuit with buffered outputs on both phases. The circuit generates two non-overlapping clock signals from a single-phase input clock signal of up to 10MHz. Each output clock signal drives a 0.33pF load without degradation. The circuit is designed using a Sky130nm process design kit and simulated in HSpice at 10MHz. Results show the two-phase clock signals have some glitches that could be improved by adding more buffering on the outputs. The proposed circuit design will be implemented in an eSim electronic design automation tool.

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yasaswi sony
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75 views1 page

131 Literature Survey Report

This paper proposes a new robust non-overlapping two-phase clock generator circuit with buffered outputs on both phases. The circuit generates two non-overlapping clock signals from a single-phase input clock signal of up to 10MHz. Each output clock signal drives a 0.33pF load without degradation. The circuit is designed using a Sky130nm process design kit and simulated in HSpice at 10MHz. Results show the two-phase clock signals have some glitches that could be improved by adding more buffering on the outputs. The proposed circuit design will be implemented in an eSim electronic design automation tool.

Uploaded by

yasaswi sony
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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A Two-Phase Non-Overlapping Clock Generator With Buffered

Output
Polasi Yasaswi, Swami Vivekananda Institute of Technology

June 21, 2021

Abstract 2 Reference Circuit

In this paper, a new robust non overlapping two phase


clock generator with buffered output on both phases is
proposed. Two phase clock is a control signal gener-
ator and bus driver which must perform well driving
relatively large capacitive loads. A two phase clock of-
fers a great deal of freedom in sequential circuit design
if the clock period and the duration of the signals p1
and p2 are correctly chosen. The circuit lodged here
uses a pMOS, nMOS transistors. Result reflects that Figure 1: Reference circuit diagram.
the proposed approach shows a H Spice simulation re-
sult at 10MHz. The proposed circuit will implemented
in eSim EDA tool and will be done using Sky130nm 3 Reference Circuit Waveforms
PDK

1 Reference Circuit Details

The circuit two phase clock generator is required to ac-


cept a single-phase input clock signal of 10MHz max-
imum frequency and, from this, generate two phase
non overlapping clock signals at the input clock fre-
quency. The two-phase clock signals are to be good,
clean square waves, and each phase should be capable
of driving a load capacitance of 0.33pF without un- Figure 2: Reference waveform.
due waveform degradation. The design rules used in
two-phase clock generator circuit will be lambda based
with value lambda = 2 micro meters for fabrication
References
in single poly, single metal, p well CMOS technology. [1] S. E. Kamran Eshraghian, Douglas A.Pucknell.
All transistors are of minimum size that is W = L = Essentials of vlsi circuits and systems.
2 lambda. The observations made are, the amount of https://www.researchgate.net/profile/Dr-
underlap between the p1 and p2 waveforms is barely Ghanshyam-Singh/publication/256194556_Two-
adequate, p1 output rises faster than p2 peak voltage Phase_Clocking_Scheme_for_Low-
does not quite reach 5V owing to the time required for Power_and_High-S.
the Nor gate to rise. The square waves produced at
each output are not particularly good and there is a [2] R. T. D. U. of Technology and K. I. C. E.
noticeable glitch on the p2 output. If larger capaci- T. R. Life Sciences in Bydgoszcz. Mul-
tive loads are required to be driven, such as an output tiphase programmable clock generator.
with associated off chip wiring, then two possibilities https://www.researchgate.net/publication/224699242_035_mm
are, Increase the number of cascaded inverter buffers
at each output and if the technology in use caters for
BiCMOS circuits, the redesign the two phase generator
to include BiCMOS output stages for each phase. A
futher need may be for buffered complementary out-
puts, that is complement of p1 nd compliment of p2 to
be generated.

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