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DD Lab Exp-4-5 (DE10-Lite)

The document describes a student's work on logic circuit design assignments in Verilog. It includes the truth tables and diagrams for a half adder and full adder circuit. It also provides the Verilog code for a half adder, full adder, and 4-bit parallel adder. The student further provides Verilog code and testbenches for additional assignments on converting between binary and gray code, and designing a full subtractor using different modeling approaches.

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RollingRage
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113 views20 pages

DD Lab Exp-4-5 (DE10-Lite)

The document describes a student's work on logic circuit design assignments in Verilog. It includes the truth tables and diagrams for a half adder and full adder circuit. It also provides the Verilog code for a half adder, full adder, and 4-bit parallel adder. The student further provides Verilog code and testbenches for additional assignments on converting between binary and gray code, and designing a full subtractor using different modeling approaches.

Uploaded by

RollingRage
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

Run 1: Half adder


A half adder is a circuit capable of adding two 1-bit numbers to produce a 1-bit sum and a 1-bit
carry. Write down the truth table of a half adder and draw its diagram
Diagram

(Please refer to the procedure Appendix-II for the first time to understand the software flow.
Later the same procedure is to be followed.)

Truth Table:

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

Verilog Code

module half_adder (sum, carry,a,b);


input a,b;
output sum,carry;
assign sum = a^b;
assign carry = a & b;
endmodule

Truth Table

a b sum carry

0 0

0 1

1 0

1 1
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

output photos:
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

Run 2: Full adder and 4-bit adder


A. Write the Verilog code of Full adder using data flow modeling.
(Hint: Sum = A^B^C, Carry = C(A^B) + AB)

A: Verilog Code-
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

Truth Table

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

B. Write the Verilog code for 4- bit parallel adder using structural modeling, use full adder as a
building block defined in above code file.
(This is using or calling module from another file)

B: Verilog Code-
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

Assignment All assignments are to be submitted strictly before start of next lab session through
online only. Late assignments will not be entertained and will be awarded ‘0’ marks.
Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

1. Verilog code and testbench for converting 8-bit binary number to gray code using data
flow modeling.
Ans:https://edaplayground.com/x/mevF

: Paste the Image of your EPWave window

2. Verilog code and testbench for full subtractor using data flow modeling.
Ans: https://edaplayground.com/x/EtXF

: Paste the Image of your EPWave window


Name & ID:…Syed Afraz 2022A7PS0142U…………………………………

3. Verilog code and testbench for full subtractor using behavioral modeling.
Ans: https://edaplayground.com/x/vDpe

: Paste the Image of your EPWave window

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