Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
Timing and Control:
The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers in the system including the flip-flops
and registers in the control unit. The clock pulses do not change the state of a register unless the
register is enabled by a control signal. The control signals are generated in the control unit and
provide control inputs for multiplexers in the common bus, control inputs in processor registers,
and Microoperation for the accumulator. There are two major types of control organizations
hardwired control and microprogrammed control. In the hardwired organization, the control logic
is implemented with gates, flip-flops, decoders, and other digital circuits. It has the advantage that
it can be optimized to produce a fast mode of operation. In the micro-programmed organization,
the control information is stored in the control memory. The control memory is programmed to
initiate the required sequence. A hardwired control, as the name implies, requires changes in the
wiring among the various components if the design has to be modified or changed. In the
microprogrammed control, any required changes or modifications can be done by updating the
microprogramming in the control memory. A hardwired control for the basic computer is presented
here. The block diagram of the control unit is shown in the figure below;
Other options
15 14 13 12 11-0
3x8
I Decoder
7 6543210
D0
D7 Control
. Logic Control
. Gates Outputs
T15
.
.
T0 .
.....
15 14 2 1 0
4 x 16
Decoder
4-bit sequence Increment (INR)
Counter SC Clear (CLR)
Clock
Figure: Control unit of basic computer
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
It consists of two decoders, a sequence counter, and a number of control logic gates. An instruction
read from memory is placed in the instruction register IR, the position of this register in the common bus
system. This instruction register is divided into three parts: The I-bit, the operation code, and bits (0)
through (11). The opcode in bits (12) through (14) is decoded with a 3x8 decoder. The eight outputs of
the decoder are designated by the symbols D0 through D7.
The subscripted decimal number is equivalent to the binary value of the corresponding operation
code. Bit 15 of the instruction is transferred to a flip-flop designated by the symbol (I). Bits (0) through
(11) are applied to the control logic gates. The 4-bit sequence counter can count in binary from (0) through
(15). The outputs of the counter are decoded into 16 timing signals T0 through T15. The sequence counter
SC can be incremented or cleared synchronously. Most of the time, the counter is incremented to provide
the sequence of timing signals out of the 4 x 16 decoder. As an example, consider the case where SC is
incremented to provide timing signals T0, T1, T2, T3, and T4 in sequence. At time Ti SC is cleared to (0) if
decoder output D3 is active. This is expressed symbolically by the statement:
D3T4 : SC 0
For example, the register transfers statement below:
T0 : AR PC
Specifies a transfer of the content of the PC into AR if timing signal T0 is active. T0 is active during an
entire clock cycle interval. During this time the content of the PC is placed onto the bus (with S2S1S0 =
010) and the LD (load) input of AR is enabled. The timing diagram of Fig. 5-7 shows the time relationship
of the control signals. The sequence counter SC responds to the positive transition of the clock. Initially,
the CLR input of SC is active. The first positive transition of the clock clears SC to 0, which in tum
activates the timing signal T0 out of the decoder. T0 is active during one clock cycle.
The positive clock transition abled connected T0 in the diagram will trigger only those registers
whose control inputs are transition, to timing signal T0. SC is incremented with every positive clock unless
transition unless its CLR input is active. This produces the sequence of timing signals T0. T1, T2, T3, T4,
and so on, as shown in the diagram. (Note the relationship between the timing signal and its corresponding
positive clock transition.) If SC is not cleared, the timing signals will continue with T5, T6, up to T15, and
back to T0
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
The last three waveforms in Fig. 5-7 show how SC is cleared when D3T4 = I. Output D3
from the operation decoder becomes active at the end of timing signal T2• When timing signal T4
becomes active, the output of the AND gate that implements the control function D3T4 becomes
active. This signal is applied to the CLR input of SC. On the next positive clock transition (the one
marked T, in the diagram) the counter is cleared to 0. This causes the timing signal T0 to become
active instead of T5 which would have been active if SC were incremented instead of cleared. A
memory read or write cycle will be initiated with the rising edge of a timing signal. It will be
assumed that a memory cycle time is less than the clock cycle time.
According to this assumption, a memory read or write cycle initiated by a timing signal
will be completed by the time the next clock goes through its positive transition. The clock
transition will then be used to load the memory word into a register. This timing relationship is not
valid in many computers because the memory cycle time is usually longer than the processor clock
cycle. In such a case it is necessary to provide wait cycles in the processor until the memory word
is available. To facilitate the presentation, we will assume that a waiting period is not necessary
for the basic computer. To fully comprehend the operation of the computer, it is crucial that one
understands the timing relationship between the clock transition and the timing signals.
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
For example, the register transfer statement
T0: AR PC
specifies a transfer of the content of the PC into AR if timing signal T0 is active. T0 is active during
an entire clock cycle interval During this time the content of the PC is placed onto the bus (with
525150 = 010) and the LD (load) input of AR is enabled. The actual transfer does not occur until
the end of the clock cycle when the clock goes through a positive transition. This same positive
clock transition increments the sequence counter SC from 0000 to 0001. The next clock cycle has
T1 active and T0 inactive.
Instruction Cycle:
A program residing in the memory unit of the computer consists of a sequence of instructions. The
program is executed in the computer by going through a cycle for each instruction. Each instruction
cycle in turn is subdivided into a sequence of sub-cycles or phases. In the basic computer, each
instruction cycle consists of the following phases:
1-Fetch an instruction from memory.
2-Decode the instruction.
3-Read the effective address from memory if the instruction has an indirect address.
4-Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to fetch, decode and execute the
next instruction. This process continues indefinitely unless a HALT instruction is encountered.
Fetch and Decode:
Initially, the program counter PC is loaded with the address of the first instruction in the
program. The sequence counter SC is cleared to (0), providing a decoded timing signal T0. After
each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T0,
T1, T2, and so on. The fetch and decode phases can be specified by the following register transfer
statements
T0 : AR PC
T1 : IR M[AR], PC PC + 1
T2 : D0 ,..., D7 Decode IR (12 - 14), AR IR(0 - 11), I IR(15)
Since only AR is connected to the address inputs of memory, it is necessary to transfer the
address from PC to AR during the clock transition associated with timing signal T0. The instruction
read from memory is then placed in the instruction register IR with the clock transition associated
with signal T1. At the same time, PC is incremented by one to prepare it for the address of the next
instruction in the program. At T2, the opcode in IR is decoded, the indirect bit is transferred to flip-
flop (I) and the address part of the instruction is transferred to AR. Note that SC is incremented
after each clock pulse to produce the sequence T0, T1, and T2
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
Type of Instructions:
The figure below presents an initial configuration for the instruction cycle and shows how
the control determines the equal to (1) if the opcode is equal to binary (111) and if D7 =1. The
instruction must be a register-reference or input-output type if D7=0 the opcode must be one of the
other seven values (000) through (110), specifying a memory-reference instruction control then
inspects the value of the first bit of the instruction which is now available in flip-flop I. if D7 =0
and I=1. We have a memory-reference instruction with an indirect address. It is then necessary to
read the effective address from memory. The microoperation for the indirect address condition can
be symbolized by the register transfer statement:
AR M[AR]
Initially, AR holds the address part of the instruction. This address is used during the
memory read operation. The word at the address given by AR is read from memory and placed on
the common bus. The LD input of AR is then enabled to receive the indirect address that resided
in the 12 least significant bits of the memory word.
Register-Reference Instructions:
Register-reference instructions are recognized by the control when D7 =1 and I=0. These
instructions use bits (0) through (11) of the instruction code to specify one of (12) instructions.
These 12 bits are available in IR (0-11). They were also transferred to AR during time T2. The
control functions and the register-reference instructions are listed in the table below:
Execution of Register-Reference Instruction
D7 IT3 = r (Common to all register-reference instructions)
IR(i)=Bi [bit in IR(0-11) that specifies the operation]
r : SC 0 Clear SC
CLA rB11 : AC 0 Clear AC
CLE rB10 : E 0 Clear E
CMA rB9 : AC AC Complement AC
CME rB8 : E E Complement E
CIR rB7 : AC Shr AC, AC(15) E, E AC(0) Circulate right
CIL rB6 : AC shl AC, AC(0) E, E AC(15) Circulate left
INC rB5 : AC AC + 1 Increment AC
SPA rB4 : If (AC(15) = 0) then (PC PC + 1) Skip if positive
SNA rB3 : If (AC(15) = 1) then (PC PC + 1) Skip if negative
SZA rB2 : If (AC = 0) then (PC PC + 1) Skip if AC zero
SZE rB1 : If (E = 0) then (PC PC + 1) Skip if E is zero
HLT rB0 : S 0 (S is a start - stop flip - flop) Halt computer
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
These instructions are executed with the clock transition associated with timing variable T3. Each
D IT
control function needs the Boolean relation 7 3 , which designates for convenience by the
symbol (r). The control function is distinguished by one of the bits in (IR) (0-11). By assigning,
the symbol (Bi) to bit (IR) all control functions can be simply denoted by (rBi). The first seven
register-reference instructions perform clear, complement, circular shift, and increment micro-
operations on the AC or E registers. The next four instructions cause a skip of the next instruction
in sequence when a stated condition is satisfied. The skipping of the instruction is achieved by
incrementing the PC once again. The condition control statements must be recognized as part of
the control conditions. The AC is positive when the sign bit in AC(15) = 0 it is negative when
AC(15) =1. The content of AC is zero (AC = 0) if all the flip-flops of the register are zero. The
HLT instruction clears a start-stop flip-flop (S) and stops the sequence counter from counting. To
restore the operation of the computer, the start-stop flip-flop must be set manually.
Memory-Reference Instructions:
The table below lists the seven memory-reference instructions. The decoded O/P Di for i = 0, 1, 2,
3, 4, 5, and 6 from the operation decoder that belongs to each instruction is in the address register.
AR was placed there during timing signal T2 when I=0, during timing signal T2 when I=0, or during
timing signal T3 when I=1. The execution of the memory-reference instructions starts with timing
signal T4 we now explain the operation of each instruction and list the control functions needed
for their execution.
Symbol Opcode Symbolic Description
AND D0 AC AC M[AR]
ADD D1 AC AC + M[AR], E Cout
LDA D2 AC M[AR]
STA D3 M[AR] AC
BUN D4 PC AR
BSA D5 M[AR] PC, PC AR + 1
M[AR] M[AR] + 1
ISZ D6
If M[AR] + 1 = 0 then PC PC + 1
1)AND to AC: This is an instruction that performs the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The result of the operation is transferred
to AC. That execute this instruction are
D0T4 : DR M[AR]
D0T5 : AC AC DR, SC 0
The control function for this instruction uses the operation decoder D0 since this output of the
decoder is active when the instruction has an AND operation whose binary code value is 000. Two
timing signals are needed to execute the instruction. The clock transition associated with timing
T4 transfers the operand from memory into DR. The clock transition associated with the next
timing signal T5 transfers to AC as the result of the AND logic operation between the contents of
DR and AC. The same clock transition clears SC to 0, transferring control to timing signal T0 to
start a new instruction cycle.
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
2) ADD to AC:
This instruction adds the content of the memory word specified by the effective address to the
value of AC. The sum is transferred into AC and the output carry Cout is transferred to the E (extended
accumulator) flip-flop. The needed to execute this instruction are
D1T4 : DR M[AR]
D1T5 : AC AC + DR, E Cout, SC 0
The same two timing signals, T4 and T5 are used again but with operation decoder D1 instead of D0, which
was used for the AND instruction. After the instruction is fetched from memory and decoded, only one
output of the operation decoder will be active, and that O/P determines the sequence that the control
follows during the execution of a memory-reference instruction.
3) LDA: load to AC This instruction transfers the memory word specified by the effective address to AC.
The needed to execute this instruction are:
D 2 T4 : DR M[AR]
D 2 T5 : AC DR, SC 0
Looking back at the bus system previously, we note that there is no direct path from the bus to AC. The
address and logic circuit Receive information from DR which can be transferred into AC. Therefore, it is
necessary to read memory words into DR first 7 then transfer the content of DR into AC. The reason for
not connecting the bus to the inputs of AC is the delay encountered in the adder and logic circuit
4) STA: Store AC
This instruction stores the content of AC into a memory word specified by the effective address. Since the
O/P of AC is applied to the bus and the data I/P of memory is connected to the bus, we can execute this
instruction with one microoperation.
D3T4 : M[AR] AC, SC 0
5) BUN: Branch Unconditionally
This instruction allows the programmer to specify an instruction out of sequence and say that the program
branches (or jumps) unconditionally. The instruction is executed with one microoperation:
D4T4 : PC AR, SC 0
The effective address from AR is transferred through the common bus to PC. Resetting SC to 0
transfers control to T0, the next instruction is then fetched and executed from the memory address given
by the new value in PC. Remember that PC holds the address of the instruction to be read from memory
in the next instruction cycle PC is incremented at time T1 to prepare it for the address of the next instruction
in the program sequence.
6) BSA: Branch and Save Return Address
This instruction is useful for branching to a portion of the program called a subroutine or procedure. When
executed the BSA instruction stores the address of the next instruction in sequence (which is available in
PC) into a memory location specified by the effective address. The effective address plus one is then
transferred to the PC to serve as the address of the first instruction in the subroutine. This operation was
specified with the following register transfer:
M[AR] PC, PC AR + 1
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
7) ISZ: Increment and Skip if Zero
This instruction increments the word specified by the effective address, and if the incremented value is
equal to 0, PC is incremented by 1. The programmer usually stores a negative number (in 2’s complement)
in the memory word. As this negative number is repeatedly incremented by one, it eventually reaches the
value of zero. At that time, PC is incremented by one in an address to skip the next instruction in the
program. Since is not possible to increment a word inside the memory it is necessary to read into DR,
increment DR and store the word back into memory. This is done with the following sequence:
D6T4 : DR M[AR]
D6T5 : DR DR + 1
D6T6 : M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0
Example: A numerical example that demonstrates how BSA instruction is used with a subroutine
is shown in figure below:
20
0 BSA 135 20 0 BSA 135
PC=21 Next instruction 21 Next instruction
AR=135 135 21
Subroutine PC = 136 Subroutine
1 BUN 135 1 BUN 135
(a): Memory, PC & AR at time T4 (b): Memory & PC after execution
Example of BSA instruction execution
The BSA instruction is assumed to be in memory at address 20. The bit I is 0 and the address part of the
instruction has the binary equivalent of 135. after the fetch and decode phases, PC contains 21, which is
the address of the next instruction in the program (referred to as return address AR holds the effective
address 135. this is shown in part (a) of the figure. The BSA instruction performs the following numerical
operation:
M[135] 21, PC 135 + 1 = 136
The result of this operation is shown in part (b) of the figure above. The return address 21 is stored in
memory location 135 and control continues with the subroutine program starting from address 136. The
return to the original program (at address 21) is accomplished by means of an indirect BUN instruction
placed at the end of the subroutine. When this instruction is executed, the control goes to the indirect phase
to read the effective address to location 135, where it finds the previously saved address 21. When the
BUN instruction is executed, the effective address 21 is transferred to the PC.
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Computer Architecture
Baghdad University
Asst. Prof. Dr. Muna Hadi Third stage
College of Engineering
2023-2024
Electrical Engineering Department
Lecture-7
The next instruction cycle finds a PC with the value 21, so control continues to execute the instruction at
the return address. It is not possible to perform the operation of the BSA instruction in one clock when we
use bus system of the basic computer. To use the memory and the bus properly, the BSA instruction must
be executed with the sequence of two micropoerations,
D5T4 : M[AR] PC, AR AR + 1
D5T5 : PC AR, SC 0
Timing signal T4 initiates a memory write operation places the content of PC onto the bus and enables the
INR input of AR. The memory write operation is completed and AR is incremented by the time the next
clock transition occurs. The bus is used at T5 to transfer the content of AR to PC.
Control Flowchart:
A flowchart showing all the execution of the seven memory-reference instructions is shown in the
figure below. The microperations that are performed during times T4, T5, and T6 depend on the operation
code value. Note that we need only seven timing signals to execute the longest instruction (ISZ).
AND ADD LDA STA
D0T4 D1T4 D2T4 D3T4
D0T5 D1T5 D2T5
BUN BSA ISZ
D4T4 D5T4 D6T4
D6T5
D5T5
D6T6
Flowchart for memory-
reference instruction
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