High Isolation, Silicon SPDT,

Nonreflective Switch, 0.1 GHz to 6.0 GHz

Data Sheet HMC8038
FEATURES FUNCTIONAL BLOCK DIAGRAM

16 NC

15 NC

14 NC

13 NC
Nonreflective, 50 Ω design
High isolation: 60 dB typical
Low insertion loss: 0.8 dB typical
HMC8038
High power handling VDD 1 12 RF2
34 dBm through path 50Ω
VCTL 2 11 GND
29 dBm terminated path 50Ω
High linearity RFC 3 10 GND
0.1 dB compression (P0.1dB): 35 dBm typical
NC 4 9 RF1
Input third-order intercept (IP3): 60 dBm typical
ESD ratings PACKAGE

13554-001
BASE

NC 8
NC 7
4 kV human body model (HBM), Class 3A

EN 5

NC 6
1.25 kV charged device model (CDM)
Single positive supply Figure 1.
3.3 V to 5 V
1.8 V-compatible control
All off state control
16-lead, 4 mm × 4 mm LFCSP (16 mm2)
Pin compatible with the HMC849ALP4CE

APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Automotive telematics
Mobile radios
Test equipment

GENERAL DESCRIPTION
The HMC8038 is a high isolation, nonreflective, 0.1 GHz to single, positive voltage control from 0 V to 1.8 V/3.3 V/5.0 V at
6.0 GHz, silicon, single-pole, double-throw (SPDT) switch in a very low dc currents. An enable input (EN) set to logic high
leadless, surface-mount package. The switch is ideal for cellular places the switch in an all off state, in which RFC is reflective.
infrastructure applications, yielding up to 62 dB of isolation up to The HMC8038 has ESD protection on all device pins, including
4.0 GHz, a low 0.8 dB of insertion loss up to 4.0 GHz, and 60 dBm the RF interface, and can stand 4 kV HMB and 1.25 kV CDM.
of input third-order intercept. Power handling is excellent up to The HMC8038 offers very fast switching and RF settling times of
6.0 GHz, and it offers an input power for an 0.1 dB compression 150 ns and 170 ns, respectively. The device comes in a RoHS-
point (P0.1dB) of 35 dBm (VDD = 5 V). On-chip circuitry operates compliant, compact 4 mm × 4 mm LFCSP.
a single, positive supply voltage from 3.3 V to 5 V, as well as a

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
HMC8038 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Interface Schematics .....................................................................6
Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7
Functional Block Diagram .............................................................. 1 Insertion Loss, Isolation, and Return Loss ................................7
General Description ......................................................................... 1 Input Compression and Input Third-Order Intercept .............8
Revision History ............................................................................... 2 Theory of Operation .........................................................................9
Specifications..................................................................................... 3 Applications Information .............................................................. 10
Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 11
ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 11
Pin Configuration and Function Descriptions ............................. 6

REVISION HISTORY
11/15—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3

9/15—Revision 0: Initial Version

Rev. A | Page 2 of 11
Data Sheet HMC8038

SPECIFICATIONS
VDD = 3.3 V to 5 V, VCTL = 0 V/VDD, TA = 25°C, 50 Ω system, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INSERTION LOSS 0.1 GHz to 2.0 GHz 0.7 1.0 dB
2.0 GHz to 4.0 GHz 0.8 1.1 dB
4.0 GHz to 6.0 GHz 0.9 1.3 dB
ISOLATION 0.1 GHz to 2.0 GHz 55 70 dB
RFC to RF1/RF2 (Worst Case) 2.0 GHz to 4.0 GHz 50 60 dB
4.0 GHz to 6.0 GHz 40 51 dB
RETURN LOSS
On State 0.1 GHz to 2.0 GHz 24 dB
2.0 GHz to 4.0 GHz 18 dB
4.0 GHz to 6.0 GHz 18 dB
Off State 0.1 GHz to 2.0 GHz 23 dB
2.0 GHz to 4.0 GHz 22 dB
4.0 GHz to 6.0 GHz 16 dB
SWITCHING SPEED
tRISE, tFALL 10%/90% RFOUT 60 ns
tON, tOFF 50% VCTL to 10%/90% RFOUT 150 ns
RF SETTLING TIME 50% VCTL to 0.1 dB margin of final RFOUT 170 ns
INPUT POWER
1 dB Compression (P1dB) VDD = 3.3 V 34 dB
VDD = 5 V 36 dB
0.1 dB Compression (P0.1dB) VDD = 3.3 V 33 dB
VDD = 5 V 35 dB
INPUT THIRD-ORDER INTERCEPT (IP3) Two-tone input power = 14 dBm/tone 60 dBm
RECOMMENDED OPERATING CONDITIONS
Bias Voltage Range (VDD) 3.0 5.4 V
Control Voltage Range (VCTL, EN) 0 VDD V
Maximum RF Input Power 1
TCASE = 105°C Through Path (5 V/3.3 V) 31/30 dBm
Terminated Path 24 dBm
Hot Switching 24 dBm
TCASE = 85°C Through Path (5 V/3.3 V) 34/33 dBm
Terminated Path 27 dBm
Hot Switching 27 dBm
TCASE = 25°C Through Path (5 V/3.3 V) 34/33 dBm
Terminated Path 29 dBm
Hot Switching 27 dBm
TCASE = −40°C Through Path (5 V/3.3 V) 34/33 dBm
Terminated Path 29 dBm
Hot Switching 27 dBm
Case Temperature Range (TCASE) −40 +105 °C
1
Exposure to levels between the recommended operating conditions and the absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 3 of 11
HMC8038 Data Sheet
Table 2. Digital Control Voltages
State VDD = 3.3 V (±5% VDD, TCASE = −40°C to +105°C) VDD = 5 V (±5% VDD, TCASE = −40°C to +105°C)
Input Control Voltage
Low (VIL) 0 V to 0.85 V at <1 µA, typical 0 V to 1.20 V at <1 µA, typical
High (VIH) 1.15 V to 3.3 V at <1 µA, typical 1.55 V to 5.0 V at <1 µA, typical

Table 3. Bias Voltage vs. Supply Current

Parameter Symbol Min Typ Max Unit Typical IDD (mA)
SUPPLY CURRENT IDD
VDD = 3.3 V 0.14 mA 0.14
VDD = 5 V 0.16 mA 0.16

Rev. A | Page 4 of 11
Data Sheet HMC8038

ABSOLUTE MAXIMUM RATINGS

During the through mode of operation, the supply voltage scales
Table 4. the maximum allowed input power. The power handling vs.
Parameter Rating frequency for the 3.3 V and 5 V supplies is shown in Figure 2.
Bias Voltage Range (VDD) −0.3 V to +5.5 V 40
Control Voltage Range (VCTL, EN) −0.5 V to VDD + (+0.5 V)
RF Input Power1 (see Figure 2)
Through Path 35 dBm
35
Terminated Path 30 dBm

INPUT POWER (dBm)

Hot Switching 30 dBm
Channel Temperature 135°C
30
Storage Temperature Range −65°C to +150°C
Thermal Resistance (Channel to Package
Bottom)
Through Path 110°C/W 25
Terminated Path 100°C/W AMR
OPERATING 5V
ESD Sensitivity OPERATING 3.3V
HBM 4 kV (Class 3A) 20

13554-002
CDM 1.25 kV 0 1 2 3 4 5 6
FREQUENCY (GHz)
1
For recommended operating conditions, see Table 1.
Figure 2. Through Path, Power Handling vs. Frequency
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a ESD CAUTION
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 5 of 11
HMC8038 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16 NC
15 NC
14 NC
13 NC
VDD 1 12 RF2
VCTL 2 HMC8038 11 GND
TOP VIEW
RFC 3 (Not to Scale) 10 GND
NC 4 9 RF1

NC 8
NC 7
EN 5
NC 6
NOTES
1. NC = NO CONNECT. THE PINS ARE NOT CONNECTED
INTERNALLY; HOWEVER, ALL DATA SHOWN HEREIN WAS
MEASURED WITH THESE PINS CONNECTED TO RF/DC

13554-003
GROUND EXTERNALLY.
2. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO
RF/DC GROUND.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 VDD Supply Voltage Pin.
2 VCTL Control Input Pin. See Figure 5 for the VCTL interface schematic. Refer to Table 6 and the recommended input
control voltage range in Table 2.
3 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
4, 6 to 8, NC Not Internally Connected. These pins are not internally connected; however, all data shown in this data sheet is
13 to 16 measured with the NC pins externally connected to RF/dc ground on the evaluation board.
5 EN Enable Input Pin. See Figure 5 for the EN interface schematic. Refer to Table 6 and the recommended input
control voltage range in Table 2.
9 RF1 RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
10, 11 GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB)
RF ground. See Figure 4 for the GND interface schematic.
12 RF2 RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin.
EPAD Exposed Pad. Exposed pad must be connected to RF/dc ground.

INTERFACE SCHEMATICS
GND
Table 6. Truth Table
13554-004

Control Input Signal Path State

VCTL State EN State RFC to RF1 RFC to RF2
Figure 4. GND Interface Schematic Low Low Off On
VDD High Low On Off
Low High Off Off
13554-005

VCTL, EN
High High Off Off
Figure 5. Logic Control Interface Schematic

Rev. A | Page 6 of 11
Data Sheet HMC8038

TYPICAL PERFORMANCE CHARACTERISTICS

INSERTION LOSS, ISOLATION, AND RETURN LOSS
0 0

–0.5 –0.5

INSERTION LOSS (dB)

INSERTION LOSS (dB)

–1.0 –1.0

–1.5 –1.5

+105°C +105°C
+85°C +85°C
–2.0 +25°C –2.0 +25°C
–40°C –40°C

–2.5 –2.5

13554-009
13554-006
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 6. Insertion Loss vs. Frequency over Temperatures, VDD = 5 V Figure 9. Insertion Loss vs. Frequency over Temperatures, VDD = 3.3 V

0 0

RF1 RFC TO RF1 ON

RF2 –10 RFC TO RF2 ON
–20 ALL OFF
–20
ISOLATION (dB)
ISOLATION (dB)

–30
–40

–40

–60 –50

–60
–80
–70

–100 –80

13554-010
13554-007

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 7. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 3.3 V to 5 V Figure 10. Isolation Between RF1 and RF2 vs. Frequency at VDD = 3.3 V to 5 V

–5

–10
RETURN LOSS (dB)

–15

–20

–25

–30

RFC
–35 RF1, RF2 OFF
RF1, RF2 ON
–40
13554-008

0 1 2 3 4 5 6 7
FREQUENCY (GHz)

Figure 8. Return Loss vs. Frequency at VDD = 3.3 V to 5 V

Rev. A | Page 7 of 11
HMC8038 Data Sheet
INPUT COMPRESSION AND INPUT THIRD-ORDER INTERCEPT
40 40

38 38
INPUT COMPRESSION (dBm)

INPUT COMPRESSION (dBm)

36 36

34 34

32 32

30 +105°C 30 +105°C
+85°C +85°C
+25°C +25°C
28 –40°C 28 –40°C

26 26

13554-014
13554-011
0 1 2 3 4 5 6 0 1 2 3 4 5 6
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 11. Input Compression 1 dB Point vs. Frequency over Temperature, Figure 14. Input Compression 0.1 dB Point vs. Frequency over Temperature,
VDD = 5 V VDD = 5 V
40 40

+105°C
38 38 +85°C
+25°C
–40°C
INPUT COMPRESSION (dBm)

INPUT COMPRESSION (dBm)

36 36

34 34

32 32

30 +105°C 30
+85°C
+25°C
28 –40°C 28

26 26
13554-012

13554-015
0 1 2 3 4 5 6 0 1 2 3 4 5 6
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 12. Input Compression 1 dB Point vs. Frequency over Temperature, Figure 15. Input Compression 0.1 dB Point vs. Frequency over Temperature,
VDD = 3.3 V VDD = 3.3 V
65 65

60 60
IP3 (dBm)

IP3 (dBm)

55 55

50 +105°C 50 +105°C
+85°C +85°C
+25°C +25°C
–40°C –40°C

45 45
13554-013

13554-016

0 1 2 3 4 5 6 0 1 2 3 4 5 6
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 13. Input Third-Order Intercept (IP3) Point vs. Frequency, VDD = 5 V Figure 16. Input Third-Order Intercept (IP3) Point vs. Frequency, VDD = 3.3 V

Rev. A | Page 8 of 11
Data Sheet HMC8038

THEORY OF OPERATION
The HMC8038 requires a single-supply voltage applied to the With the EN pin is logic low, the HMC8038 has two operation
VDD pin. Bypassing capacitors are recommended on the supply modes: on and off. Depending on the logic level applied to the
line to minimize RF coupling. VCTL pin, one RF output port (for example, RF1) is set to on
The HMC8038 is controlled via two digital control voltages mode, by which an insertion loss path is provided from the
applied to the VCTL pin and the EN pin. A small bypassing input to the output, as the other RF output port (for example,
capacitor is recommended on these digital signal lines to RF2) is set to off mode, by which the output is isolated from the
improve the RF signal isolation. input. When the RF output port (RF1 or RF2) is in isolation
mode, internally terminate it to 50 Ω, and the port absorbs the
The HMC8038 is internally matched to 50 Ω at the RF input applied RF signal.
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx pins When the EN pin is logic high, the EN pin sets the HMC8038
are dc-coupled, and dc blocking capacitors are required on the switch to off mode. In off mode, both output ports are isolated
RF lines. The design is bidirectional; the input and outputs are from the input, and the RFC port is open reflective.
interchangeable.
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up the digital control inputs. The relative order of
the logic control inputs are not important. Powering the digital
control inputs before the VDD supply can inadvertently
forward bias and damage ESD protection structures.
4. Power up the RF input.

Table 7. Switch Operation Mode

Digital Control Inputs Switch Mode
VEN VCTL RFC to RF1 RFC to RF2
0 0 Off mode. The RF1 port is isolated from the RFC port and On mode. A low insertion loss path from the RFC
is internally terminated to a 50 Ω load to absorb the port to the RF2 port.
applied RF signals.
0 1 On mode. A low insertion loss path from the RFC port to Off mode. The RF2 port is isolated from the RFC port
the RF1 port. and is internally terminated to a 50 Ω load to absorb
the applied RF signals.
1 X1 All in off mode. Both the RF1 and RF2 ports are isolated from the RFC port, and the RFC port is reflective.
1
X stands for don’t care.

Rev. A | Page 9 of 11
HMC8038 Data Sheet

APPLICATIONS INFORMATION
Generate the evaluation PCB used in the application shown in Table 8. Bill of Materials for Evaluation Board
Figure 17 with proper RF circuit design techniques. Signal lines EV1HMC8038LP4C1
at the RF port must have a 50 Ω impedance, and the package
Reference Designator Description
ground leads and backside ground slug must connect directly to
J1 to J3 PCB mount SMA connector
the ground plane, as shown in Figure 18. The evaluation board
C1 to C6 100 pF capacitor, 0402 package
shown in Figure 18 is available from Analog Devices, Inc. upon
C7 0.1 μF capacitor, 0402 package
request.
R1, R2 0 Ω resistor, 0402 package
U1 HMC8038 SPDT switch
PCB2 600-01267-00 evaluation PCB
1
Reference to this evaluation board number when ordering the complete
evaluation board.
2
Circuit board material: Roger 4350 or Arlon 25FR.

VDD
C7 C4
16

13
15

14
C3
0.1µF 100pF 1 12 RF2
50Ω 100pF
VCTL 2 11 GND
C5 50Ω
3 10 GND
100pF C2
C1 4 9 RF1
100pF
RFC
8
7
5

100pF PACKAGE
C6

13554-017
BASE

EN 100pF

Figure 17. HMC8038 Application Circuit

13554-018

Figure 18. EV1HMC8038LP4C Evaluation Board

Rev. A | Page 10 of 11
Data Sheet HMC8038

OUTLINE DIMENSIONS
4.10 0.39
4.00 SQ 0.33
3.90 PIN 1
PIN 1 0.27 INDICATOR
INDICATOR (0.30)
13 16
0.65 1
BSC 12

2.55
EXPOSED 2.40 SQ
PAD
2.25
9
4

0.70 8 5
0.20 MIN
TOP VIEW 0.60 BOTTOM VIEW

0.50 1.95 REF

1.00
FOR PROPER CONNECTION OF
0.90 THE EXPOSED PAD, REFER TO
0.05 MAX
0.80 THE PIN CONFIGURATION AND
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF

08-14-2015-A
PKG-000000

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

Figure 19. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.90 mm Package Height
(CP-16-40)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range MSL Rating2 Package Description Package Option Branding 3
HMC8038LP4CE −40°C to +105°C MSL3 16-lead Lead Frame Chip Scale Package [LFCSP] CP-16-40 8038
XXXX
HMC8038LP4CETR −40°C to +105°C MSL3 16-lead Lead Frame Chip Scale Package [LFCSP] CP-16-40 8038
XXXX
EV1HMC8038LP4C −40°C to +105°C Evaluation Board
1
RoHs-Compliant Part.
2
The maximum peak reflow temperature is 260°C.
3
4-digit lot number: XXXX.

©2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D13554-0-11/15(A)

Rev. A | Page 11 of 11