High Isolation, Silicon SPDT,

Nonreflective Switch, 9 kHz to 13.0 GHz

Data Sheet HMC1118
FEATURES FUNCTIONAL BLOCK DIAGRAM

GND

GND

GND
RF1
Nonreflective 50 Ω design
Positive control: 0 V/3.3 V

16

15

14

13
Low insertion loss: 0.68 dB at 8.0 GHz
High isolation: 48 dB at 8.0 GHz GND 1 HMC1118 50Ω 12 VDD
High power handling
GND 2 11 LS
35 dBm through path
27 dBm terminated path RFC 3 10 VCTRL
High linearity
GND 4 50Ω 9 VSS
1 dB compression (P1dB): 37 dBm typical
Input third-order intercept (IIP3): 62 dBm typical

8
ESD rating: 2 kV human body model (HBM)
PACKAGE

RF2
GND

GND

GND

12961-001
3 mm × 3 mm, 16-lead LFCSP package BASE
GND
No low frequency spurious
Settling time (0.05 dB margin of final RFOUT): 7.5 μs Figure 1.

APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Fiber optics and broadband telecommunications

GENERAL DESCRIPTION
The HMC1118 is a general-purpose, broadband, nonreflective and 0 V and requires +3.3 V and −2.5 V supplies. The HMC1118
single-pole, double-throw (SPDT) switch in a LFCSP surface can cover the same operating frequency range with a single
mount package. Covering the 9 kHz to 13.0 GHz range, the positive supply voltage applied and the negative supply voltage
switch offers high isolation and low insertion loss. The switch (VSS) tied to ground and still maintaining good power handling
features >48 dB isolation, 0.68 dB insertion loss up to 8.0 GHz, performance. The HMC1118 is packaged in a 3 mm × 3 mm,
and a 7.5 μs settling time of 0.05 dB margin of final RFOUT. The surface mount LFCSP package.
switch operates using positive control voltage logic lines of +3.3 V

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
HMC1118 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6
Applications ....................................................................................... 1 Interface Schematics .....................................................................6
Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7
Revision History ............................................................................... 2 Input Compression Point and Input Third-Order Intercept ...8
Specifications..................................................................................... 3 Theory of Operation .........................................................................9
Electrical Specifications ............................................................... 3 Applications Information .............................................................. 10
Digital Control Voltages .............................................................. 4 Evaluation PCB ........................................................................... 10
Bias and Supply Current .............................................................. 4 Outline Dimensions ....................................................................... 11
Absolute Maximum Ratings ............................................................ 5 Ordering Guide .......................................................................... 11
ESD Caution .................................................................................. 5

REVISION HISTORY
10/2017—Rev. 0 to Rev. A
Change to Product Title................................................................... 1
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11

10/2015—Revision 0: Initial Version

Rev. A | Page 2 of 11
Data Sheet HMC1118

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VCTRL = 0 V/3.3 V dc, VDD = LS = 3.3 V dc, VSS = −2.5 V dc, TA = 25°C, 50 Ω system, unless otherwise specified.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INSERTION LOSS
9 kHz to 3.0 GHz 0.5 1.0 dB
9 kHz to 8.0 GHz 0.68 1.1 dB
9 kHz to 10.0 GHz 0.7 1.3 dB
9 kHz to 13.0 GHz 1.3 2.0 dB
ISOLATION RFC TO RF1/RF2 (WORST CASE)
9 kHz to 3.0 GHz 40 50 dB
9 kHz to 8.0 GHz 42 48 dB
9 kHz to 10.0 GHz 28 35 dB
9 kHz to 13.0 GHz 18 25 dB
RETURN LOSS
On State 9 kHz to 3.0 GHz 26 dB
9 kHz to 8.0 GHz 22 dB
9 kHz to 13.0 GHz 9 dB
Off State 9 kHz to 3.0 GHz 26 dB
9 kHz to 8.0 GHz 14 dB
9 kHz to 13.0 GHz 5 dB
RADIO FREQUENCY (RF) SETTLING TIME
50% VCTRL to 0.05 dB margin of final RFOUT 7.5 µs
50% VCTRL to 0.1 dB margin of final RFOUT 6 µs
SWITCHING SPEED
tRISE/tFALL 10%/90% RF 0.85 µs
tON/tOFF 50% VCTRL to 10%/90% RF 2.7 µs
INPUT POWER 1 MHz to 13.0 GHz
1 dB Compression (P1dB) 35 37 dBm
0.1 dB Compression (P0.1dB) 35 dBm
INPUT THIRD-ORDER INTERCEPT (IIP3) Two-tone input power = 14 dBm at each tone, 1 MHz to 13.0 GHz 62 dBm
RECOMMENDED OPERATING CONDITIONS 1
Positive Supply Voltage (VDD) 3.0 3.6 V
Negative Supply Voltage (VSS) −2.75 −2.25 V
Control Voltage (VCTRL) Range 0 VDD V
Logic Select (LS) Voltage Range 0 VDD V
RF Input Power VDD/VCTRL = 3.3 V, VSS = −2.5 V, TA = 85°C, frequency = 2 GHz
Through Path 35 dBm
Termination Path 27 dBm
Hot Switch Power Level VDD = 3.3 V, TA = 85°C, frequency = 2 GHz 27 dBm
Case Temperature Range (TCASE) −40 +85 °C
1
These are the recommended values for these parameters.

Rev. A | Page 3 of 11
HMC1118 Data Sheet
DIGITAL CONTROL VOLTAGES
VDD = 3.3 V ± 10%, VSS = −2.5 V ± 10%, TCASE = −40°C to +85°C, unless otherwise specified.

Table 2.
Parameter Symbol Min Typ Max Unit Test Condition/Comments
INPUT CONTROL VOLTAGE <1 µA typical
Low VIL −0.3 +0.8 V
High VIH 2.0 VDD + 0.3 V

BIAS AND SUPPLY CURRENT

Table 3.
Parameter Symbol Min Typ Max Unit
SUPPLY CURRENT
VDD = 3.3 V IDD 20 200 µA
VSS = −2.5 V ISS 0.5 10 µA

Rev. A | Page 4 of 11
Data Sheet HMC1118

ABSOLUTE MAXIMUM RATINGS

4

Table 4.
0
Parameter Rating
Positive Supply Voltage (VDD) Range −0.3 V to +3.7 V dc –4
Negative Supply Voltage (VSS) Range −2.8 V to +0.3 V

POWER (dB)
Control Voltage (VCTRL) Range −0.3 V to VDD + 0.3 V –8

Logic Select (LS) Voltage Range −0.3 V to VDD + 0.3 V

–12
RF Input Power1 (VDD/VCTRL = 3.3 V, VSS = −2.5 V, See Figure 2 to
TA = 85°C, Frequency = 2 GHz) Figure 4
–16
Through Path 37 dBm
Termination Path 28 dBm –20
Hot Switch Power Level (VDD = 3.3 V, 30 dBm
TA = 85°C, Frequency = 2 GHz) –24

12961-004
0.01 0.1 1 10 100 1000
Storage Temperature Range −65°C to +150°C FREQUENCY (MHz)
Maximum Reflow Temperature (MSL3 Rating) 260°C Figure 3. Power Derating Through Path (Low Frequency Detail)
Channel Temperature 135°C
4
Thermal Resistance (Channel to Package
Bottom) 0
Through Path 116°C/W
Terminated Path 100°C/W –4

ESD Sensitivity (HBM), Class 2 2 kV

POWER (dB) –8
1
For recommended operating conditions, see Table 1.
–12
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a –16
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational –20
section of this specification is not implied. Operation beyond
–24
the maximum operating conditions for extended periods may

12961-003
0.01 0.1 1 10 100 1000 10000
affect product reliability. FREQUENCY (MHz)

Figure 4. Power Derating for Hot Switching Power

4
ESD CAUTION
0

–4
POWER (dB)

–8

–12

–16

–20

–24
12961-002

0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (GHz)

Figure 2. Power Derating Through Path

Rev. A | Page 5 of 11
HMC1118 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

GND

GND
RF1
16

15

14

13
GND 1 12 VDD

GND 2
HMC1118 11 LS
TOP VIEW
RFC 3 (Not to Scale) 10 VCTRL

GND 4 9 VSS

8
GND

GND

GND
RF2
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED

12961-005
TO THE RF/DC GROUND OF THE PRINTED
CIRCUIT BOARD (PCB).

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 4 to 6, 8, 13, 15, 16 GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit
board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic.
3 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if
the RF line potential is not equal to 0 V dc.
7 RF2 RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
14 RF1 RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
9 VSS Negative Supply Voltage Pin.
10 VCTRL Control Input Pin. See Table 1, Table 2, and Table 6.
11 LS Logic Select Input Pin. See Table 1, Table 2, and Table 6.
12 VDD Positive Supply Voltage Pin.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the printed circuit board (PCB).

Table 6. Truth Table

Control Input Signal Path State
LS VCTRL RFC to RF1 RFC to RF2
High Low On Off
High High Off On
Low Low Off On
Low High On Off

INTERFACE SCHEMATICS
VDD

GND
LS
12961-008
12961-006

Figure 6. GND Interface Schematic Figure 8. LS Interface Schematic

VDD

VCTRL
12961-007

Figure 7. VCTRL Interface Schematic

Rev. A | Page 6 of 11
Data Sheet HMC1118

TYPICAL PERFORMANCE CHARACTERISTICS

INSERTION LOSS, RETURN LOSS, AND ISOLATION
0 0

–10

–20
–1
INSERTION LOSS (dB)

–30

ISOLATION (dB)
–40
–2
–50

–60
–3
–70
TA = +85°C
TA = +25°C –80
RF1
TA = –40°C RF2
–4 –90

12961-009

12961-010
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 9. Insertion Loss vs. Frequency Figure 11. Isolation Between RFC and the RF1 and RF2 Ports vs. Frequency

0 0
RF1, RF2 ON
RFC –10
RF1, RF2 OFF
–10 –20

–30
RETURN LOSS (dB)

ISOLATION (dB)

–20 –40

–50

–30 –60

–70

–40 –80

–90 RFC TO RF1 ON

RFC TO RF2 ON
–50 –100

12961-012
12961-011

0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
FREQUENCY (GHz) FREQUENCY (GHz)

Figure 10. Return Loss vs. Frequency Figure 12. Isolation Between RF1 and RF2 Ports vs. Frequency

Rev. A | Page 7 of 11
HMC1118 Data Sheet
INPUT COMPRESSION POINT AND INPUT THIRD-ORDER INTERCEPT
40 40

38 35
INPUT COMPRESSION (dBm)

INPUT COMPRESSION (dBm)

36 30

34 25

32 20

30 15
0.1dB COMPRESSION POINT 0.1dB COMPRESSION POINT
1dB COMPRESSION POINT 1dB COMPRESSION POINT
28 10

12961-013

12961-016
0 1 2 3 4 5 6 7 8 9 10 11 12 13 0.01 0.1 1 10 100 1000
FREQUENCY (GHz) FREQUENCY (MHz)

Figure 13. 0.1 dB and 1 dB Compression Point vs. Frequency Figure 16. 0.1 dB and 1 dB Input Compression Point vs. Frequency
(Low Frequency Detail)
40 40

38 35
INPUT COMPRESSION (dBm)

INPUT COMPRESSION (dBm)

36 30

34 25

32 20

30 15
TA = +85°C TA = +85°C
TA = +25°C TA = +25°C
TA = –40°C TA = –40°C
28 10
12961-014

12961-017
0 1 2 3 4 5 6 7 8 9 10 11 12 13 0.01 0.1 1 10 100 1000
FREQUENCY (GHz) FREQUENCY (MHz)

Figure 14. 1 dB Input Compression Point vs. Frequency over Temperature Figure 17. 1 dB Input Compression Point vs. Frequency over Temperature
(Low Frequency Detail)
65 65

60 60
INPUT IP3 (dBm)

INPUT IP3 (dBm)

55 55

50 50

TA = +85°C TA = +85°C
TA = +25°C TA = +25°C
TA = –40°C TA = –40°C
45 45
12961-015

12961-018

0 2 4 6 8 10 12 0.1 1 10 100 1000

FREQUENCY (GHz) FREQUENCY (MHz)

Figure 15. Input Third-Order Intercept (IIP3) Point vs. Frequency over Figure 18. Input Third-Order Intercept (IIP3) Point vs. Frequency over
Temperature Temperature (Low Frequency Detail)

Rev. A | Page 8 of 11
Data Sheet HMC1118

THEORY OF OPERATION
The HMC1118 requires a positive supply voltage applied to the The logic select (LS) allows the user to define the control input
VDD pin and a negative supply voltage applied to the VSS pin. logic sequence for the RF path selections. With the LS pin set to
Bypassing capacitors are recommended on the supply lines to logic high, the RFC to RF1 path turns on when VCTRL is logic
minimize RF coupling. The HMC1118 can operate with a single low, and the RFC to RF2 path turns on when VCTRL is logic high.
positive supply voltage applied to the VDD pin and the negative With LS set to logic low, the RFC to RF1 path turns on when VCTRL
voltage input pin (VSS) connected to ground; however, some is logic high, and the RFC to RF2 path turns on when VCTRL is
performance degradations in the input power compression and logic low.
third-order intercept can occur. Depending on the logic level applied to the LS and VCTRL pins,
The HMC1118 is controlled via two digital control voltages applied one RF output port (for example, RF1) is set to on mode, by
to the VCTRL pin and the LS pin. A small value bypassing capacitor which an insertion loss path provides the input to the output.
is recommended on these digital signal lines to improve the RF The other RF output port (for example, RF2) is then set to off
signal isolation. mode, by which the output is isolated from the input. When the
The HMC1118 is internally matched to 50 Ω at the RF input RF output port (RF1 or RF2) is in isolation mode, internally
port (RFC) and the RF output ports (RF1 and RF2); therefore, terminate it to 50 Ω, and the port absorbs the applied RF signal
no external matching components are required. The RF1 and (see Table 7).
RF2 pins are dc-coupled, and dc blocking capacitors are required
on the RF paths if the RF potential is not equal to a common-
mode voltage of 0 V. The design is bidirectional; the input and
outputs are interchangeable.
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD and VSS. The relative order is not important.
3. Power up the digital control inputs. The relative order of
the logic control inputs is not important. Powering the
digital control inputs before the VDD supply can inadvertently
forward bias and damage the internal ESD protection
structures.
4. Power up the RF input.

Table 7. Switch Mode Operation

Digital Control Inputs Signal Mode
LS VCTRL RFC to RF1 RFC to RF2
High Low On mode. A low insertion loss path from the RFC Off mode. The RF2 port is isolation from the RFC port and
port to the RF1 port. internally terminated to a 50 Ω load to absorb the applied
RF signals.
High High Off mode. The RF1 port is isolation from the RFC On mode. A low insertion loss path from the RFC port to the
port and internally terminated to a 50 Ω load to RF2 port.
absorb the applied RF signals.
Low Low Off mode. The RF1 port is isolation from the RFC On mode. A low insertion loss path from the RFC port to the
port and internally terminated to a 50 Ω load to RF2 port.
absorb the applied RF signals.
Low High On mode. A low insertion loss path from the RFC Off mode. The RF2 port is isolation from the RFC port and
port to the RF1 port. internally terminated to a 50 Ω load to absorb the applied
RF signals.

Rev. A | Page 9 of 11
HMC1118 Data Sheet

APPLICATIONS INFORMATION
EVALUATION PCB
Generate the evaluation PCB used in this application with
proper RF circuit design techniques. Signal lines at the RF port
must have 50 Ω impedance, and the package ground leads and
backside ground slug must be connected directly to the ground
plane similarly to what is shown in Figure 19. The evaluation
board shown in Figure 19 is available from Analog Devices, Inc.
upon request.

12961-019

Figure 19. EV1HMC1118LP3D Evaluation PCB

Table 8. Bill of Materials for the EV1HMC1118LP3D Evaluation Board1

Item Description Manufacturer2
J1 to J3 PC mount SMA RF connectors
TP1 to TP5 Through-hole hold mount test points
C1, C5 100 pF capacitors, 0402 package
U1 HMC1118 SPDT switch Analog Devices, Inc.
PCB 600-01012-00-1 evaluation PCB, Rogers 4350 circuit board material EV1HMC1118LP3D, Analog Devices, Inc.1
1
Reference this number to order the full evaluation PCB.
2
The blank cells in the manufacturer column are left blank intentionally for they are user-selectable.

Rev. A | Page 10 of 11
Data Sheet HMC1118

OUTLINE DIMENSIONS
3.10 0.30
3.00 SQ 0.25
PIN 1 2.90 0.20
INDICATOR PIN 1
INDICATOR
13 16
0.50
12 1
BSC
EXPOSED 1.92
PAD
1.70 SQ
1.48

9 4
*0.35 8 5
0.20 MIN
TOP VIEW 0.30 BOTTOM VIEW

0.25
0.95
FOR PROPER CONNECTION OF
0.85 THE EXPOSED PAD, REFER TO
0.05 MAX
0.75 THE PIN CONFIGURATION AND
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.20 REF

01-08-2015-A
PKG-000000

*COMPLIANT WITH JEDEC STANDARDS MO-220-VEED-4

WITH THE EXCEPTION OF PACKAGE EDGE TO LEAD EDGE.

Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.85 mm Package Height
(CP-16-38)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range MSL Rating 2 Package Description Package Option
HMC1118LP3DE −40°C to +85°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-38
HMC1118LP3DETR −40°C to +85°C MSL3 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-38
EV1HMC1118LP3D Evaluation Board
1
HMC1118LP3DE and HMC1118LP3DETR are RoHS-Compliant Parts.
2
See the Absolute Maximum Ratings section.

©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D12961-0-10/17(A)

Rev. A | Page 11 of 11