Practice Set -1 for COA ETE Examination
Q.1 Find the address bus size of a digital system with a memory specification of 2048 kilobytes.
Q.2 How many multiplexers are needed, and what will be the size of each multiplexer, to create a
common bus for a digital system with 64 registers, where each register is 8 bits?
Q.3 The computer's memory unit consists of 128 K words, each comprising 32 bits. The computer
utilizes an instruction format characterized by four fields: an operation code, a mode field determining
one of the 9 addressing modes, a register field designating one of the 28 processor registers, and a
memory address. Specify the instruction format and the bit count for each field when the instruction is
contained within a single memory word.
Q.4 A computer employs a memory unit comprising 1024 K words, each consisting of 64 bits. A binary
instruction code is stored in a single word of memory, comprising four components: an indirect bit, an
operation code, a register code section specifying one of 128 registers, and an address part. Illustrate
the instruction word format and specify the bit count for each component.
Q.5 Create a flowchart algorithm for performing addition and subtraction operations on signed-
magnitude numbers.
Q.6 Identify the addressing mode commonly associated with the following:
a) Branch-type instructions
b) Accessing operands in an array
c) Relocating programs in memory
Additionally, explain the method for determining the effective address in each of these modes.
Q.7 Design a 4-bit Adder/ Subtractor using parallel adder.
Q.8 In the basic computer, where the Program Counter (PC) holds the value 3AF and the Accumulator
(AC) contains 7EC3, the memory content at address 3AF is 932E. Subsequently, the content of memory
at address 932E is 09AC, and the content of memory at address 09AC is 8B9F. What instruction will
be fetched and executed? Also, show the contents of PC, AR, IR, DR, AC and SC after the execution of
the instruction?
Q.9 Show the contents of registers E, A, Q and SC during the process of multiplication of two binary
numbers 11111 (multiplicand) and 10101 (multiplier). The signs are not included.
Q.10 Show the contents of registers E, A, Q, and SC during the process of division of 10100011 by
1011 using restoring method of division.
Q.11 Draw the flowchart for instruction cycle and depict all the micro-operations of all phases of the
instruction cycle.
Q.12 Design and explain the working of 4-bit Arithmetic Circuit.
Q.13 Perform multiplication of 4-bit numbers using Booth's Algorithm for the following two cases: (a)
(-15) X (+10) (b) (+15) X (-10)
Q.14 Explain the various addressing modes with the help of a numerical example.
Q.15 Provide justification through a program to evaluate a specific expression, explaining the necessity
for distinct instruction formats in various processor organizations that are three- address instruction,
two-address instruction, one-address instruction, and zero address instruction.
Q.16 Design an array multiplier that multiplies two 4-bit numbers. Use AND gates and binary address.
Q.17 What is the value of output of a 4- bit combination circuit shifter, if input A is 1010, S=1. In this
particular circuit, S=0 is for right shift and S=1 for left shift, Input right bit (IR)= 0, and Input Left bit
(IL) = 1. How the logical shift is different from circular shift and arithmetic shift micro-operation?
Q.18 Design an array multiplier that multiplies two 4-bit numbers.
Q.19 The 8-bit register AR, BR, CR and DR initiatory have the following values. AR = 10010010,
BR = 11111111, CR = 10101001 and DR = 10101010.Determine the 8-bit values in each register of
the execution of the following sequence of micro-operations.
(i) AR<-AR + BR
(ii) CR<- CR Λ DR, BR<- BR + 1
(iii) AR<-AR – CR
Q.20 Distinguish between restoring and non-restoring division method. Perform binary division when
dividend =11 and divisor = 3 using non-restoring method.
