📘 CMOS Layout Design & Stick Diagram –
Detailed Notes
1. Introduction
CMOS design flow:
Logic Design → Circuit Design → Layout Design → Fabrication.
Layout Design: Physical representation of a circuit on silicon, showing layers (diffusion,
polysilicon, metal, contacts, wells).
Ensures circuit is fabrication-ready.
2. Layers in CMOS Layout
1. Active Layer (Diffusion): Region where transistors form.
2. Polysilicon Layer: Forms transistor gates and interconnects.
3. Metal Layer(s): For routing signals and power supply.
4. Contact/Via: Connects polysilicon, metal, and diffusion regions.
5. N-Well/P-Well: Defines regions for NMOS/PMOS transistors.
📌 Insert Figure 1: Typical CMOS layout layers.
3. Design Rules
Ensure layout is manufacturable with good yield.
Governed by Design Rule Check (DRC).
Rules include:
o Minimum line width
o Minimum spacing between layers
o Overlap requirements
Expressed in terms of λ (lambda-based rules) → scalable across technologies.
4. Layout of CMOS Inverter
Steps:
1. Place PMOS in N-Well and NMOS in P-substrate.
2. Connect gates using polysilicon.
3. Connect drains of PMOS and NMOS together → output.
4. Connect PMOS source to VDD (metal) and NMOS source to GND (metal).
📌 Insert Figure 2: Layout of CMOS inverter.
5. Stick Diagram
A simplified layout representation using colored/line symbols.
Captures topology without exact dimensions.
Useful for manual design planning.
Symbols:
o Diffusion → green line
o Polysilicon → red line
o Metal → blue line
o Contact → black square
o N-Well → dotted lines
📌 Insert Figure 3: Stick diagram symbols.
6. Stick Diagram of CMOS Inverter
Steps:
1. Draw NMOS and PMOS using diffusion lines.
2. Place polysilicon line (gate) crossing both.
3. Connect drains together (output).
4. Connect sources to VDD and GND.
Result: Simplified schematic for layout planning.
📌 Insert Figure 4: Stick diagram of CMOS inverter.
7. Layout Design Styles
1. Full Custom Design: Each transistor and interconnect optimized (high performance).
2. Standard Cell Design: Uses pre-designed, tested cells for efficiency.
3. Gate Array: Prefabricated transistor array customized by metal routing.
8. Verification in Layout Design
DRC (Design Rule Check): Ensures layout follows rules.
LVS (Layout vs Schematic): Ensures layout matches circuit schematic.
ERC (Electrical Rule Check): Detects floating nodes, shorts.
9. Advantages of Stick Diagrams
Fast sketching of circuit topology.
Simplifies manual layout planning.
Reduces design errors before full layout.
10. Applications
Used in VLSI design training.
Helps in floor planning and layout optimization.
Widely used in ASIC and microprocessor design process.
