ON Semiconductor

Is Now

To learn more about onsemi™, please visit our website at

www.onsemi.com

onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
 Is Now Part of

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
 www.fairchildsemi.com

Application Note AN6032

FAN4800 Combo Controller Applications
General Description The PFC Stage
This application note shows the step-by-step process to
design a high-performance supply. The equations shown in Powering the FAN4800
this document can also be used for different output voltages The FAN4800 is initialized once C12 is charged to 13V
and total power. through R27 and R28. PFC switching action boosts the volt-
The complete power supply circuits shown in Figures 6 and age on C5 to 380V via L1’s inductance. T2 then supplies a
7 demonstrate the FAN4800’s ability to manage high output well-regulated 13V for the FAN4800 from its secondary
power while complying with international requirements winding. T2’s primary-to-secondary turns ratio (NPRI /
regarding AC line quality. The PFC section provides NSEC) is 18.8:1. For proper circuit operation, high-frequency
380VDC to a dual-transistor current-mode forward converter. bypassing with low-ESR ceramic or film capacitors on VCC
The output of the converter delivers +12V at up to 8.4 amps. and VREF is provided. Orderly PFC operation upon start-up
The circuit operates from 85 to 265VAC with both power sec- is achieved when D2 quick charges the boost capacitor to the
tions switching at 100kHz. peak AC line voltage before the boost switch Q1 is turned
on. This ensures the boost inductor current is zero before

D2 D3
1N5406 D1
L1 RGF1J
F1 ISL9R460P2
3.15A
BR1
VDC / +380V
4A, 600V
KBL06
AC INPUT C1 Q1G Q2G
R1A Q1
85 TO 265Vac 0.68uF 500k Q2
R2A FQPF9N50 C5 R7A R17
R27 C4 33 FQPF
453k 100uF 178k
75k 10nF 6N50
450V
D9 R30
C25 4.7k
ISENSE MBRS D5
0.1uF
R21 140 RGF1J
R5D R2B 22
R5C 1.2 453k R28
R5B 1.2 R1B 240
R5A 1.2 500k T1B D7
1.2 C3 R7B MMBZ5245B
0.1uF C12
R3 178k
10uF
110k C30 35V
330uF
25V
C2
0.47uF
R4 Q3G
15.4k T2
R14
33 Q3 D6
R6 FQPF6N50 RGF1J
41.7k
C20
R10 1uF
6.2k
R15 RAMP2 / DC ILIMIT
C7 3
NOT USED R20A R20B
C6 2.2 2.2
R12
71.5k 1.5nF
R31 T1A R19
100 220

U1 R9
FAN4800 1.1k

1 16 Q4
IEAO VEAO MMBT3904
VFB D4
2 15
IAC VFB MMBZ5245B
R13
3 14 10k
ISENSE VREF VREF

4 13
VRMS VCC
VCC
5 12
SS PFC OUT

6 11 R11
VDC PWM OUT 845k
C10
15uF
RAMP1
7 10 D8 R16
RAMP1 GND D10 10k
MBRS
140 MBRS
8 9 C16 C14 C9
140
RAMP2 DC ILIMIT 1uF 1uF 10nF
D12 R8 C15 C13 C8
C31
1N5401 2.37k 10nF 0.1uF 68nF
1nF

C26 C19 C18

D13
1N5401
100nF 1uF 470pF VDC
C11 C17
10nF 220pF

PRI GND

Figure 1. The PFC Stage

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800 Rev. 1.0.2 • 12/07/06
AN6032 APPLICATION NOTE

PFC action begins. The value of the regulated voltage on C5

must always be greater than the peak value of the maximum
VO − 2Vin( rms _ min)
line voltage delivered to the supply. D= ( 6)
VO
VC 5 > 2Vin( rms _ max) D × 2Vin( rms _ min)
L1 = (7)
VC 5 > ( 1.414 ) × ( 265 ) (1) f S × ΔI
VC 5 > 375V use 380V
=
(VO )
− 2Vin( rms _ min) ⋅ Vin( rms _ min)2 ⋅ η
VO ⋅ f S ⋅ dI ⋅ PO(max)
Because the FAN4800 uses transconductance amplifiers, the
loop compensation networks are returned to ground (see the =
{380 − (1.414 ) ⋅ ( 85 )} ⋅ ( 85 ) ⋅ (0.95 )
2

FAN4800 datasheet for the error amplifier characteristics/ ( 380 ) ⋅ (1 × 105 ) ⋅ (0.15 ) ⋅ (100 )
advantages). This eliminates the interaction of the resistive = 3.128mH use 3.0mH
divider network with the loop compensation capacitors, per-
mitting a wide choice of divider values chosen to minimize The boost diode D1 and switch Q1 are chosen with a reverse
amplifier offset voltages due to input bias currents. For reli- voltage rating of 500V to safely withstand the 380V boost
able operation, R7A and R7B must have a voltage rating of at potential. The maximum Q1 RMS current is obtained by
least 400 volts. Equation 8 and the maximum Q1 peak current is calculated
by Equation 9.
Calculate the divider ratio (R7A+R7B)/R8 by:
1 4 2Vin( rms _ min)
R7 A + R7 B VC 5 I Q1rms = 2I in( rms _ max) −
= −1 2 3π VO
R8 2.5
R7 A + R7 B 380 2PO(max) 1 4 2Vin( rms _ min)
= −1 ( 2) = − (8)
R8 2.5 ηVin( rms _ min) 2 3π VO
R7 A + R7 B
= 151 =
(1.414 ) ⋅ ( 100 ) 1
−
4 ⋅ ( 1.414 ) ⋅ ( 85 )
R8 ( 0.95 ) ⋅ ( 85 ) 2 3 ⋅ ( 3.1416 ) ⋅ ( 380 )
= 1.06 A
Selecting the Power Components
ΔI
The FAN4800 PFC section operates with continuous induc- I Q1 peak = I in( peak _ max) +
2
tor current to minimize peak current and to maximize avail-
able power. The boost inductor value found by setting ΔI, the
=
2PO(max)
+
(VO )
− 2Vin( rms _ min) ⋅ 2Vin( rms _ min)
peak-to-peak value of high-frequency current, is typically ηVin( rms _ min) VO ⋅ f S ⋅ L1 (9)
10% to 20% of the peak value of the maximum line current.
=
(1.414 ) ⋅ (100 ) + {380 − ( 1.414 ) ⋅ ( 85 )} ⋅ (1.414 ) ⋅ ( 85 )
2Pin(max) (0.95 ) ⋅ ( 85 ) ( 380 ) ⋅ (1 × 105 ) ⋅ ( 3 × 10 −3 )
I in( peak _ max) =
Vin( rms _ min)
( 3)
= 2.025A
PO(max)
Pin(max) = ( 4) The boost diode average current can be calculated by:
η
I D1avg = I O(max)
where Iin(peak_max) is a peak value of input current occurred PO(max)
= (10 )
at low line, Vin(rms_min) is RMS value of minimum line volt- VO
age, PO(max) is the maximum output power, and η is effi- 100
ciency. Value Iin(peak_max) defines value of ΔI, where dI is = = 0.26 A
380
the specified percentage rate. IL(max) is the inductor maxi-
mum current. The boost capacitor value is chosen to permit a given output
voltage hold-up time in the event the line voltage is suddenly
ΔI = dI × I in( peak _ max) ( 5) removed.
ΔI 2PO(max)tHLD
I L(max) = I in( peak _ max) +
2 C5 ≥
VC 5( NOM )2 − VC 5( MIN )2
(11)

Duty cycle D and switching frequency fS influence inductor where:

selection.
tHLD = hold-up time (sec)
VC5(min) = minimum voltage on C5 at which the PWM stage
can still deliver full output power
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800 Rev. 1.0.2 • 12/07/06 2
AN6032 APPLICATION NOTE

A key advantage of using leading/trailing-edge modulation

is that a large portion of the inductor current is "dumped"
kM
directly into the load (PWM stage transformer) and not the k= (16 )
boost capacitor. This relaxes the ESR requirement of the Vrms 2
boost capacitor. For reference, Equation 12 should be used as kM = kVin( rms _ min)2 (16a )
a starting point when choosing C5’s maximum ripple current = ( 0.35 ) ⋅ ( 85 )
2

rating (at 120Hz).

= 2528.75 ≈ 2529
IO( C5 )
I C5 _ rms = (12 ) 3. Select the value of (R1A+R1B) that permits the greatest
2
(I peak = 2 ⋅ IC5 _ rms ) (12a )
multiplier output current without saturating the output.
The maximum output current of the multiplier is
228.57μA.
Selecting the Power Setting Components k 2Vin( rms _ min) (VEAO(max) − 0.625 )
The maximum average power delivered by the PFC stage is ( R1A + R1B ) ≥
228.57 × 10 −6
set using the following procedure: (0.35 ) ⋅ (1.414 ) ⋅ ( 85 )(6 − 0.625 )
( R1A + R1B ) ≥ (17 )
1. Find the resistive divider ratio that results in the voltage 228.57 × 10 −6
at the VRMS pin being equal to 1.14V at the lowest line ( R1A + R1B ) ≥ 989.38kΩ use 1M Ω
voltage. The voltage at this pin must be well filtered, yet
able to respond well to transient line voltage changes.
4. Select the value of the current sense resistor to complete
R4 1.14 ⋅ π the calculations for the power setting components.
=
RTOT 2 2Vin( rms _ min)
(13)
RMULO ⋅ kM (VEAO(max) − 0.625 ) ⋅ η
R5 A || R5 B || R5C || R5 D ≤ (18)
PO(max) ( R1A + R1B )
The resistor and capacitor values in the typical example
were found empirically to offer the lowest ripple voltage R5 A || R5 B || R5C || R5 D ≤
( 3.5 × 10 ) ⋅ ( 2529 )(6 − 0.625 ) ⋅ (0.95 )
3

and still respond well to line voltage changes. Should a (100 ) (1 × 10 ) 6

ratio be required that is greatly different from that found R5 A || R5 B || R5C || R5 D ≤ 0.452Ω use 0.3Ω
in Equation 13, adjust the filter capacitor values accord-
ing to Equations 14 and 15.
where:
RTOT
C3 = (14 ) RMULO = multiplier output termination resistance (3.5kΩ).
2π f 1 ⋅ ( R2 A + R2 B ) ⋅ ( R3 + R4 )
⎛ R4 ⋅ RTOT ⎞ Voltage Loop Compensation
⎜⎜ 1 + ⎟
( 2 A 2 B ) ( 3 4 ) ⎟⎠
R + R ⋅ R + R
C2 = ⎝ (15) Maximum transient response of the PFC section, without
2π f 2 ⋅ R4 instability, is obtained when the open-loop crossover fre-
quency is one-half the line frequency. For this application,
where: the compensation components (pole/zero pair) are chosen so
f1 = 15Hz, f2 = 23Hz that the closed loop response decreases at 20dB/decade,
crossing unity gain at 30Hz, then immediately decreasing at
RTOT = R2A + R2B + R3 + R4 40dB/decade. The error amplifier pole is placed at 30Hz and
an effective zero at one-tenth this frequency, or 3Hz. Find
the crossover frequency (GPS = 1) of the power stage. For
2. Find the constant of proportionality kM of the multiplier reference, Equation 20 finds the power stage pole and Equa-
gain k in Equation 16a. To obtain "brownout" action tion 21 finds the power stage DC gain.
below the lowest input voltage, the maximum gain of the
multiplier must be used when finding kM. The maximum
gain (0.35) occurs when the VRMS input of the multiplier
is 1.14V. Equation 16 is the general expression for the
multiplier gain versus the line voltage.

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 3
AN6032 APPLICATION NOTE

VBOOST R8
GRDIV = ( 23)
R7 A + R7 B + R8
R7 2.37
FB
=
178 + 178 + 2.37
VEAO
= 6.613 × 10 −3 ( −43.59dB )
15
16
R8 2.5V R11
C9 The amount of error amplifier gain required to bring the
C8 open-loop gain to unity at 30Hz is the negative of the sum of
the power stage, plus divider stage gain (attenuation):

GEA = − ( GPS( 30 Hz ) + GRDIV ) ( 24 )

Figure 2. Voltage Amp Compensation
= − ( 8.736 + ( −43.59 ) )

Pin(max)
= 34.854dB ( 55.29V / V )
fC =
2π VO (VEAO(max) − 0.625 ) C5
The value of R11, which sets the high-frequency gain of the
PO(max) error amplifier, can be determined by:
= (19 )
2πηVO (VEAO(max) − 0.625 ) C5
GEA
100 R11 = ( 25 )
= gM
( 2 ) ⋅ ( 3.1416 ) ⋅ (0.95 ) ⋅ ( 380 ) ⋅ (6 − 0.625 ) ⋅ (100 × 10 −6 ) 55.29
= 82.02Hz =
70 × 10 −6
= 789.8k Ω use 845kΩ
1
fP = ( 20 ) Calculate C8; which, together with R11, sets the zero fre-
π RLC5
1 quency at 3Hz.
=
( 3.1416 ) ⋅ (1444 ) ⋅ (100 × 10 −6 ) 1
C8 = ( 26 )
= 2.20Hz 2π R11 f Z
1
=
where: ( 2 ) ⋅ ( 3.1416 ) ⋅ ( 845 × 103 ) ⋅ ( 3)
VO 2 = 62.8nF use 68nF
RL =
PO(max)
Since the pole frequency is ten times the zero frequency, the
pole capacitor C9 is one-tenth the value of C8.
2 fC
GPS ( DC ) = ( 21) C8
fP C9 = ( 27 )
=
(1.414 ) ⋅ ( 82.02 ) 10
2.20 68 × 10 −9
=
= 52.72 ( 34.44dB ) 10
= 6.8nF use 10nF
The gain of the power stage at 30Hz is calculated by:
Current Loop Compensation
fC
GPS( 30 Hz ) = ( 22 ) The current loop is compensated like the voltage loop,
30
82.02 except the choice of the open-loop crossover frequency. To
= prevent interaction with the voltage loop, the current loop
30
= 2.734 ( 8.736dB ) bandwidth should be greater than ten times the voltage loop
crossover frequency, but no more than one sixth the switch-
ing frequency, or 16.7kHz. The power stage crossover fre-
The power stage gain is attenuated by the resistive divider
quency is calculated by Equation 28, the pole frequency by
(R7A+R7B)/R8 according to Equation 23:
Equation 29, and the power stage DC gain by Equation 30.

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 4
AN6032 APPLICATION NOTE

GEA
R12 R12 = ( 33)
VREF g M ( CE )
14
C7
7.58
GND 3.5k =
10
VREF C6 85 × 10 −6
VEAO 1 = 89.2k Ω use 71.5k Ω
IEAO
IAC
R5A R5B R5C R5D
3.5k
Calculate the value of C6 to form the zero at 1.67kHz.
3 1
ISENSE C6 =
2π R12 f Z
( 34 )
Figure 3. Current Amp Compensation 1
=
( 2 ) ⋅ ( 3.1416 ) ⋅ (71.5 × 103 ) ⋅ (1.67 × 103 )
( R5 A || R5B || R5C || R5D )VO = 1.33nF use 1.5nF
fC = ( 28 )
2π L1VRAMP( P−P )
The pole capacitor C7 is one-tenth the value of C6.
=
(0.3)( 380 )
( 2 ) ⋅ ( 3.1416 ) ⋅ ( 3 × 10−3 ) ⋅ ( 2.75 ) C7 =
C6
( 35)
= 2.2kHz 10
1.5 × 10 −9
=
10
1
fP =
π RLC5
( 29 ) = 150 pF

1
=
( 3.1416 ) ⋅ (1444 ) ⋅ (100 × 10−6 ) The PWM Stage
= 2.20Hz same as (20)
Soft-Starting the PWM Stage
2 fC The FAN4800 features a dedicated soft-start pin for control-
GPS( DC ) = ( 30 ) ling the rate of rise of the output voltage and preventing
fP
overshoot during power on. The controller does not initiate
(1.414 ) ⋅ ( 2.20 × 103 )
= soft-start action until the PFC voltage reaches its nominal
2.20 value, thereby preventing stalling of the output voltage due
= 1414 ( 63.0dB ) to excessive PFC currents. PWM action is terminated in the
event the FAN4800 loses power or if the PFC boost voltage
Find the gain of the power stage at 16.7kHz. falls below 228VDC. The soft-start capacitor value (C19) for
50ms of delay is found by Equation 36.
fC
GPS( 16.7 kHz ) = ( 31)
16.7 × 10 3 ⎛ 20 × 10 −6 ⎞
2.20 × 10 3
C19 = ( tSS ) ⋅ ⎜ ⎟ ( 36 )
= ⎝ 0.95 ⎠
16.7 × 10 3
⎛ 20 × 10 −6 ⎞
= 1.32 × 10 −1 ( −17.60dB ) = ( 0.05 ) ⋅ ⎜ ⎟
⎝ 0.95 ⎠
= 1μ F
The current loop contains no attenuating resistors, so find the
error amplifier gain with:
Setting the Oscillator Frequency
GEA = − ( −GPS( 16.7 kHz ) ) ( 32 )
= − ( −17.60 )
There is one version of the FAN4800. The FAN4800IN is
where the PFC and PWM run at the same frequency.
= 17.60dB (7.58V / V )
FAN4800IN
Determine the value of the current error amplifier setting
resistor R12. In general, it is best to choose a small-valued capacitor C18
to maximize the oscillator duty cycle (minimize the C18 dis-
charge time). Too small a value capacitor can increase the
oscillator’s sensitivity to phase modulation caused by stray
field voltage induction into this node. For the practical

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 5
AN6032 APPLICATION NOTE

D3
RGF1J

VDC / +380V

Q2G
C5 R17 Q2
R7A
100uF 33 FQPF
178k
450V 6N50
R30
C25 4.7k
0.1uF D5
RGF1J

T1B D7 12V
D11A
R7B MMBZ5245B MBR2545CT L2
C12
178k 12V,
10uF
35V 100W
C24
D11B 1uF
MBR2545CT C21
2200uF
Q3G 25V
T2
R14
33 Q3 D6
R6 FQPF6N50 RGF1J R24 R18
41.7k 1.2k 220
C20
R10 1uF
6.2k
R15 RAMP2 / DC ILIMIT
C7 3
NOT USED R20A R20B R23 C22 R22
C6 2.2 2.2 1.5k 4.7uF 8.66k
R12
71.5k 1.5nF U2
T1A R19 MOC8112
220

U1 R9
FAN4800 1.1k

1 16 Q4
IEAO VEAO MMBT3904
VFB R26 C23
D4
2 15 10k 100nF
IAC VFB MMBZ5245B
R13
3 14 10k
ISENSE VREF VREF U3
TL431A
4 13 R25
VRMS VCC 2.26k 12V RET
VCC
5 12 12V
SS PFC OUT
RETURN
6 11 R11
VDC PWM OUT 845k
C10
15uF
7 10 D8 R16
RAMP1 GND D10 10k
MBRS
140 MBRS
8 9 C16 C14 C9
140
RAMP2 DC ILIMIT 1uF 1uF 10nF

R8 C31 C15 C13 C8

2.37k 1nF 10nF 0.1uF 68nF

C19 C18
1uF 470pF VDC
C11 C17
10nF 220pF

PRI GND

Figure 4. The PWM Stage

example, a 470pF capacitor is chosen for C18. Equation 37 is Voltage Mode (Feedforward)
accurate with values of R6 greater than 10k.
Should voltage mode control be used, it is necessary to know
1 C5’s peak voltage to choose the correct ramp generating
R6 ≅ ( 37 )
0.51 ⋅ f SW C18 components. Equation 39 finds the worst-case peak-to-peak
1 ripple voltage across C5. To find the peak voltage, divide the
≅
(0.51) ⋅ (1 × 105 ) ⋅ ( 470 × 10 −12 ) ripple voltage by two and add it to the regulated boost volt-
age. Remember that since the FAN4800 employs leading/
≅ 41.7k Ω trailing modulation, the actual peak-to-peak ripple voltage is
generally much less than the calculated value.
Current Limit 2
⎛ 1 ⎞
The PWM power stage operates in current mode using R20A VR( C 5 ) = I OUT ( C 5 ) ⎜ ⎟ + ESR ( C5 )
2
( 39 )
and R20B to generate the voltage ramp for duty cycle control. ⎝ 4π f LC5 ⎠
The FAN4800 limits the maximum primary current via an
internal 1V comparator; which, when exceeded, terminates where:
the drive to the external power MOSFETs. Maximum pri- fL = line frequency.
mary current is:
Solve Equation 40 for the ramp resistor value. The ramp
1 capacitor value should be in the range of 470pF ~ 10nF.
I PRI ( MAX ) = ( 38)
R20 A || R20 B Choose a resistor with an adequate voltage rating to with-
2.2 + 2.2 stand the boost voltage.
=
2.2 × 2.2
= 0.91Amps

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 6
AN6032 APPLICATION NOTE

Output Voltage Compensation

σ ( MAX ) A TL431 shunt regulator U3 and opto-isolator U2 perform
RRAMP =
⎛
C RAMP f SW ln ⎜ 1 −
VREF ⎞ ( 40 ) output voltage setting and regulation. The opto crosses the
⎟ primary-to-secondary safety boundary, varying the voltage
⎝ VO + 0.5V R ⎠
on the VDC pin to keep the output voltage constant against
line and load changes. Using current-mode control simplifies
where:
loop compensation, leaving only a single pole and zero in the
σ(MAX) = maximum PWM duty cycle output stage. The pole is created from the output capacitor
(0.45 for the FAN4800) and equivalent load resistance. The zero is formed from the
filter capacitor and its ESR. In this example, the action of the
VR = peak-to-peak boost capacitor ripple voltage for
zero occurs well after the closed-loop response has crossed
Equation 39.
unity, so it was not compensated with a pole. The output pole
The Power Transformer Turns Ratio is canceled, increasing the overall bandwidth by the addition
of R26 and C23, which form a zero with TL431. For more
The minimum output voltage at the secondary of T2 is found information on using the TL431, including gain/phase versus
in Equation 41. The secondary voltage is chosen to be 30 frequency characteristics, refer to the Fairchild Semiconduc-
volts to increase the output voltage hold-up time. tor datasheet for the TL431.
VOUT
VSEC( MIN ) = + VF ( 41) 3.3V Output Design Changes
σ ( MAX )
12 The latest microprocessors and support circuitry require a
= + 1.0 3.3V supply for proper operation. The FAN4800 is ideal for
0.45
= 27.7Volts these applications, including the energy-efficient, ecologi-
cally friendly "Green" PC. If the total output power required
The transformer turns ratio is derived from Equation 42: varies greatly from 100 watts, it is necessary to re-select cer-
tain components, beginning with the PFC stage. T2’s turn
N PRI VO ratio must be adjusted according to Equation 42 and another
= ( 42 )
N SEC VSEC( MIN ) low-current secondary winding added using the same turns
380 ratio as originally found for the +12 volts. This second wind-
=
30 ing is necessary to power the TL431/opto circuit because the
N PRI : N SEC = 38 : 3 3.3V output is not adequate to fully bias the feedback cir-
cuitry. C21 may be increased to reduce the output ripple volt-
The maximum secondary current with the output shorted is age. Figure 5 displays a 3.3V output stage capable of
limited by Equation 43: supplying 16 amps.

I PRI ( MAX ) N PRI

I SEC( MAX ) = ( 43) UF4001
N SEC

=
(0.91) ⋅ ( 38 )
3 L2 VOUTPUT
= 11.5Amps 3.3V, 16A
D11A
C24
The output inductor and rectifier are chosen with maximum D11B C21

current rating larger than the maximum secondary current. T2

Output Filter Component Filter Selection R23 C22

R22
10.2k

L2’s value is chosen to efficiently minimize output ripple U2

MOC8112

current, thereby easing the ESR requirement of the filter

capacitor. C21’s ESR value is the dominant contributor to the
output ripple. The maximum ESR value required is found in
Equation 44: R26 C23

VR L2 f SW
( 44 )
U3
ESR( C 21 ) ≤ TL431A R25
VSECσ ( MAX ) 31.6k

where:
VR = peak-to-peak output ripple voltage. Figure 5. 3.3V Output Stage

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 7
 D2 D3
D1
AN6032

L1 1N5406 RGF1J
F1 ISL9R460P2
3.15A VDC / +380V
BR1
4A, 600V
KBL06
AC INPUT C1 Q1G Q2G
R1A Q1 NOTE : L1; PREMIER MAGNETICS TDS-1047
85 TO 265Vac 0.68uF 500k FQPF9N50 C5 R17 Q2
R2A R27 C4 R7A L2; PREMIER MAGNETICS VTP-05007
100uF 33 FQPF
453k 75k 10nF 178k T1; PREMIER MAGNETICS PMGO-03
450V 6N50
D9 R30 T2; PREMIER MAGNETICS TSO-735
C25

FAN4800 Rev. 1.0.2 • 12/07/06

MBRS 4.7k D5
ISENSE 0.1uF
R21 140 RGF1J
R5D R2B 22
R5C 1.2 R28
453k
R5B 1.2 R1B 240
R5A 1.2 500k T1B D7 12V
C3 D11A
1.2 R7B MMBZ5245B MBR2545CT L2
0.1uF C12

© 2006 Fairchild Semiconductor Corporation

R3 178k 12V,
10uF
110k C30 35V 100W
330uF
C24
25V D11B
C2 1uF
MBR2545CT C21
0.47uF
2200uF
R4 Q3G 25V
15.4k T2
R14
33 Q3 D6
R6 R24 R18
FQPF6N50 RGF1J
41.7k 1.2k 220
C20
R10 1uF
6.2k
R15
RAMP2 / DC ILIMIT
C7 3
NOT USED R20A R20B R23 C22 R22
C6 2.2 2.2 1.5k 4.7uF 8.66k
R12
71.5k 1.5nF U2

8
R31 T1A R19
MOC8112
100 220

U1 R9
FAN4800 1.1k

1 16 Q4
IEAO VEAO MMBT3904
VFB R26 C23
D4
2 15 10k 100nF
IAC VFB MMBZ5245B
R13
3 14 10k
ISENSE VREF VREF U3
TL431A
4 13 R25
VRMS VCC 2.26k 12V RET

Figure 6. Complete 100W Circuit (Current Mode)

VCC
5 12 12V
SS PFC OUT
RETURN
6 11 R11 C10
VDC PWM OUT 845k 15uF
RAMP1
7 10 D8 R16
RAMP1 GND D10 10k
MBRS
140 MBRS
C16 C14 C9
8 9 140
RAMP2 DC ILIMIT 1uF 1uF 10nF
D12 R8 C15 C13 C8
C31
1N5401 2.37k 10nF 0.1uF 68nF
1nF

C26 C19 C18

D13 100nF 1uF 470pF
1N5401
VDC
C11 C17
10nF 220pF

PRI GND

www.fairchildsemi.com
APPLICATION NOTE
 D2 D3
D1
AN6032

L1 1N5406 RGF1J
F1 ISL9R460P2
3.15A VDC / +380V
BR1
4A, 600V
KBL06
AC INPUT C1 Q1G Q2G
R1A Q1 NOTE : L1; PREMIER MAGNETICS TDS-1047
85 TO 265Vac 0.68uF 500k FQPF9N50 C5 R17 Q2
R2A R27 C4 R7A L2; PREMIER MAGNETICS VTP-05007
100uF 33 FQPF
453k 75k 10nF 178k T1; PREMIER MAGNETICS PMGO-03
450V 6N50
D9 R30 T2; PREMIER MAGNETICS TSO-735
C25

FAN4800 Rev. 1.0.2 • 12/07/06

MBRS 4.7k D5
ISENSE 0.1uF
R21 140 RGF1J
R5D R2B 22
R5C 1.2 R28
453k
R5B 1.2 R1B 240
R5A 1.2 500k T1B D7 12V
C3 D11A
1.2 R7B MMBZ5245B MBR2545CT L2
0.1uF C12

© 2006 Fairchild Semiconductor Corporation

R3 178k 12V,
10uF
110k C30 35V 100W
330uF
C24
25V D11B
C2 1uF
MBR2545CT C21
0.47uF
2200uF
R4 Q3G 25V
15.4k T2
R14
33 Q3 D6
R6 R24 R18
FQPF6N50 RGF1J
41.7k 1.2k 220
C20
R10 1uF
6.2k
R15
RAMP2 / DC ILIMIT
C7 3
NOT USED R20A R20B R23 C22 R22
C6 2.2 2.2 1.5k 4.7uF 8.66k
R12
71.5k 1.5nF U2

9
R31 T1A R19
MOC8112
100 220

U1 R9
FAN4800 1.1k

1 16 Q4
IEAO VEAO MMBT3904
VFB R26 C23
D4
2 15 10k 100nF
IAC VFB MMBZ5245B
R13
3 14 10k
ISENSE VREF VREF U3
TL431A
4 13 R25
VRMS VCC 12V RET

Figure 7. Complete 100W Circuit (Voltage Mode)

2.26k
VCC
5 12 12V
SS PFC OUT
RETURN
6 11 R11 C10
VDC PWM OUT 845k 15uF
RAMP1
7 10 D8 R16
RAMP1 GND D10 10k
MBRS
140 MBRS
C16 C14 C9
8 9 140
RAMP2 DC ILIMIT 1uF 1uF 10nF
D12 R8 C15 C13 C8
C31
1N5401 2.37k 10nF 0.1uF 68nF
1nF

C26 C19 C18 R29

D13 100nF 1uF 470pF 61.9k
1N5401
VDC

C17
C11 C27
220pF
10nF 470pF
PRI GND

www.fairchildsemi.com
APPLICATION NOTE
AN6032 APPLICATION NOTE

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1.Life support devices or systems are devices or systems which, 2.A critical component is any component of a life support device or
(a) are intended for surgical implant into the body, or system whose failure to perform can be reasonably expected to
(b) support or sustain life, or cause the failure of the life support device or system, or to affect its
(c) whose failure to perform when properly used in accordance with safety or effectiveness.
instructions for use provided in the labeling, can be reasonably
expected to result in significant injury to the user.

© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800 Rev. 1.0.2 • 12/07/06 10
 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative

© Semiconductor Components Industries, LLC www.onsemi.com www.onsemi.com

1