Skip to content
View cuitsj's full-sized avatar

Block or report cuitsj

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

CAN FD IP Core in VHDL

VHDL 70 25 Updated Aug 17, 2026

Public repository for Agent Skills

Python 170,481 20,277 Updated Aug 18, 2026

Open Source Flight Controller Firmware

C 11,437 3,983 Updated Aug 19, 2026

real time face swap and one-click video deepfake with only a single image

Python 96,009 14,000 Updated Aug 13, 2026

A visual no-code/code-free web crawler/spider易采集:一个可视化浏览器自动化测试/数据采集/网页爬虫软件,可以无代码图形化的设计和执行爬虫任务。别名:ServiceWrapper面向Web应用的智能化服务封装系统。

JavaScript 44,373 5,371 Updated Aug 19, 2026

12 Weeks, 24 Lessons, AI for All!

Jupyter Notebook 65,671 12,729 Updated Jul 21, 2026

Arduino MIPI DSI Shield

VHDL 524 163 Updated Jul 6, 2019

我设计的一个HDMI转MIPI模块,可以用于驱动各种手机屏幕当显示器用。

C 6,131 883 Updated Sep 10, 2023

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

SystemVerilog 439 80 Updated Sep 14, 2023

A FPGA friendly 32 bit RISC-V CPU implementation

Assembly 3,232 511 Updated Feb 11, 2026

Python - 100天从新手到大师

Jupyter Notebook 185,393 55,687 Updated Jul 29, 2026

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,662 367 Updated Aug 19, 2026
JavaScript 37 6 Updated Dec 24, 2021

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

C 1,386 373 Updated Feb 14, 2022

《ROS编程实操案例》

C++ 286 58 Updated Jun 27, 2022

A*最短路径规划问题(含详细注释)

Python 65 16 Updated Apr 1, 2021

Python D* Lite implementation

Python 11 3 Updated May 9, 2017

Interactive path planning with D*Lite on Raspberry Pi for Lego EV3 robots

Python 8 Updated Jan 29, 2022

Python implementation of D* Lite with interactive visualizer for grid path-planning example

Python 104 34 Updated Mar 29, 2018

Source code for article https://paul.pub/a-star-algorithm

Python 190 70 Updated Dec 30, 2018

D* Lite算法Python实现(版本1,版本2和版本3)

Python 25 5 Updated Jun 29, 2020

Lulu P swarm and P colony simulator module that allows one to import (as text file) a P colony or a P swarm (colony of P colonies) and simulate the transfer of simbolic objects.

Python 2 Updated Jan 31, 2017

VL53L0X Api port for Raspberry Pi

C 56 28 Updated Mar 25, 2019

Lua sdk for Esp32/Esp32c2/Esp32c3/Esp32c6/Esp8266/STM32L4

C 1,330 307 Updated May 30, 2024

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

5,634 799 Updated May 15, 2022

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Tcl 1,088 249 Updated Jul 13, 2026

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。

Verilog 954 266 Updated Sep 15, 2023

Numerical P system and Enzymatic Numerical P system simulator, written in Python 3 (with branch compatible for Python 2)

Python 2 1 Updated Oct 7, 2018
Next