AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Common SystemVerilog components

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

RISC-V Debug Support for our PULP RISC-V Cores

Zama's Homomorphic Processing Unit implementation on FPGA

An AXI4 crossbar implementation in SystemVerilog

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

IOPMP IP

Formal AXI verification properties from the eXpect framework for secure SoC validation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces

draft for cv32e40x integration for LiteX SoC builder

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux