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7 stars written in Verilog
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3-stage RV32IMACZb* processor with debug

Verilog 949 69 Updated Oct 28, 2025

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Verilog 296 83 Updated Oct 31, 2025

A collection of debugging busses developed and presented at zipcpu.com

Verilog 41 7 Updated Jan 18, 2024

The public repo of the AKER framework for safe and secure SoC access control systems

Verilog 9 5 Updated Jul 13, 2021

An in-chip countermeasure against static side-channel analysis attacks

Verilog 9 1 Updated Sep 11, 2025

openIPE: An Extensible Memory Isolation Framework for Microcontrollers

Verilog 7 2 Updated Oct 30, 2025

Nangate Open Cell Library

Verilog 5 1 Updated Jan 28, 2025