16-bit RISC processor model (from ALU, ICTR, RAM and Register Memory to MPU, microprogram controlled AU and CPU itself) in VHDL

Design in VHDL of an hardware component for the Logic Circuit Design course @ PoliMi

This repository contains my custom finite state machine algorithms and their corresponding testbenches, generated using TerosHDL, for robust validation.

Course assignments of COL215:- Digital Logic and System Design course at IIT Delhi under Professor Preeti Ranjan Panda

VHDL-based digital logic project from Politecnico di Milano, featuring a convolutional encoder for telecommunications. Implements a finite state machine (FSM) to process sequences from memory, doubling the number of output words.

FSM-based SPI Master implementation in VHDL with simulation and docs

Terminal access controller

Assignment 6, Digital Logic Design Lab, Spring 2021, IIT Bombay

A team-project about a fem vending-machine I had in 2nd year of uni

Automatic irrigation controller in VHDL with ASM charts, testbenches, and full Quartus + ModelSim support.

Repository for the final project of Digital Circuists from the "Reti Logiche" (Digital Circuits) course at Politecnico di Milano (AY 2020-2021)

Implementation of a low-power enconding technique.

VHDL module for histogram equalization, aiming to enhance image contrast using digital circuit design techniques in VHDL

Access Terminal in VHDL

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.

Final exam of "Logical Networks" - Polimi Computer Science Engineering - A.Y. 2022-2023

Universidade de Brasília - Teoria e Prática de Eletrônica Digital 2.

Flappy Bird VHDL

4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.

Projects done in VHDL for course at ECE TUC. Used Xilinx Software either Vivado or ISE.