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spi

Here are 42 public repositories matching this topic...

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

rafaelcalcada / rvx

RISC-V soft-core microcontroller for FPGA implementation

microcontroller cpu gpio core processor riscv spi uart mcu risc-v rv32i system-on-chip rvx zicsr

Updated Oct 18, 2025
Verilog

janschiefer / verilog_spi

A simple Verilog SPI master / slave implementation featuring all 4 modes.

asic fpga verilog spi hdl fpgas spi-master spi-slave

Updated Dec 7, 2020
Verilog

ultraembedded / core_soc

Basic Peripheral SoC (SPI, GPIO, Timer, UART)

gpio fpga timer verilog spi uart

Updated May 8, 2020
Verilog

halftop / Interface-Protocol-in-Verilog

Interface Protocol in Verilog

spi uart-verilog verilog-hdl uart-protocol

Updated Aug 2, 2019
Verilog

ultraembedded / core_spiflash

SPI-Flash XIP Interface (Verilog)

fpga verilog spi spi-flash xip axi4

Updated Oct 24, 2021
Verilog

cvonk / FPGA_SPI

Connecting FPGA and Arduino using SPI.

arduino fpga circuits spi system-verilog verilog-hdl

Updated Apr 30, 2022
Verilog

Wissance / QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Updated Nov 21, 2017
Verilog

rooinasuit / AXI_to_SPI

Designing means to communicate as an SPI master, being a part of AXI interface

fpga verilog spi systemverilog uvm functional-verification axi-lite

Updated Sep 14, 2023
Verilog

charkster / spi_slave_verilog

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

spi xilinx-fpga digilent

Updated Dec 15, 2019
Verilog

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

spi-interface rtl verilog spi hdl testbench verilog-hdl wishbone spi-master spi-protocol spi-slave verilog-project clock-generator verilog-code verilog-rtl-model wishbone-master

Updated Jul 7, 2024
Verilog

ilyajob05 / verilog_modules

verilog modules

synchronization fpga i2c memory timer verilog spi xilinx uart usart 7-segment xilinx-fpga nexys4 pll rmii nexys-4-spartan-3e nexys4-board

Updated May 4, 2020
Verilog

redchenjs / neopixel_led_controller_max10

NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器

neopixel fpga controller spi led ws2812 adafruit-neopixel ws2812b led-matrix led-strip sk6812 led-cube addressable-leds ws281x max10 apa106 led-panel

Updated Jan 4, 2022
Verilog

regymm / mit_sd_controller_improved

Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v

fpga verilog spi sdcard sdhc

Updated Dec 6, 2021
Verilog

LucAce / MachXO2-SpiPixelController

Lattice MachXO2 SPI Slave to WS2812 Pixel Controller

fpga hardware verilog spi ws2812b

Updated Jan 29, 2023
Verilog

yahia3200 / SPI-Protocol-Implementation-Using-Verilog

Implementing SPI interface using Verilog

fpga verilog spi

Updated Jul 24, 2021
Verilog

AhmedHamed3699 / AES-Encryption

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

fpga aes verilog spi aes-encryption logic-design

Updated May 19, 2023
Verilog

mcleod-ideafix / spi_master

A SPI master interface core for CPLD/FPGA

fpga verilog spi cpld

Updated Oct 8, 2018
Verilog

Ammar-Bin-Amir / SPI

RTL Design of Serial Peripheral Interface

verilog spi serial-communication rtl-design

Updated Dec 12, 2023
Verilog

ZeyadTarekk / Serial-Peripheral-Interface

Design and implement the following components of the SPI modules using verilog such that they match the requirements of the development testbench and match the SPI specifications: Master Slave Self-Checking Testbenches for the Master and Slave

master slave verilog spi digital-design

Updated Jan 6, 2022
Verilog

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