SPI master and SPI slave for FPGA written in VHDL

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Various projects of SPI loader module for xilinx fpga

A Xilinx IP Core and App for line scanner image capture and store

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

A simple SPI master

Master SPI Component written in VHDL to control an ADXL345 Accelerometer from a FPGA

The FPGA-Based FIFO

This project demonstrates how to use various communication interfaces (UART, I2C, and SPI) with PYNQ on the PYNQ-Z2 board. The project includes Vivado hardware design files and Jupyter notebook examples for each communication protocol.

SPI slave mode 0

VHDL SPI slave, providing Wishbone bus master

FPGA Digital Hardware Design

Customizable multi chip select supporting Serial Peripheral Interface master.

Development of SPI Slave driver in VHDL and SPI Master driver for STM32 in C along with 8 bit CRC calculation module to ensure data integrity.

SPI protocol in VHDL

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

This is a digital hardware design of a simple version of SPI communication protocol using VHDL as the HDL.

FSM-based SPI Master implementation in VHDL with simulation and docs