The FPGA-Based FIFO

VHDL SPI slave, providing Wishbone bus master

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

Development of SPI Slave driver in VHDL and SPI Master driver for STM32 in C along with 8 bit CRC calculation module to ensure data integrity.

This is a digital hardware design of a simple version of SPI communication protocol using VHDL as the HDL.

FSM-based SPI Master implementation in VHDL with simulation and docs

SPI protocol in VHDL

A simple SPI master

SPI Master Controller written in VHDL

SPI implementation for FPGA.

Self written SPI module in VHDL

SPI slave mode 0

This project demonstrates how to use various communication interfaces (UART, I2C, and SPI) with PYNQ on the PYNQ-Z2 board. The project includes Vivado hardware design files and Jupyter notebook examples for each communication protocol.

A Custom AXI4 SPI Peripheral

Nexys 4 DDR - Rom Controller

FPGA Digital Hardware Design

LED Wall Screen Buffer and Panel Management Controller in VHDL

SPI Master RTL on fpga. ESP32 was the slave. highly reliable, tested upto 10MHz and 512 bits for transaction length

Master SPI Component written in VHDL to control an ADXL345 Accelerometer from a FPGA

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)