This project demonstrates how to use various communication interfaces (UART, I2C, and SPI) with PYNQ on the PYNQ-Z2 board. The project includes Vivado hardware design files and Jupyter notebook examples for each communication protocol.

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

Self written SPI module in VHDL

A simple SPI master

FSM-based SPI Master implementation in VHDL with simulation and docs

The FPGA-Based FIFO

VHDL SPI slave, providing Wishbone bus master

Development of SPI Slave driver in VHDL and SPI Master driver for STM32 in C along with 8 bit CRC calculation module to ensure data integrity.

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

This is a digital hardware design of a simple version of SPI communication protocol using VHDL as the HDL.

SPI implementation for FPGA.

SPI Master RTL on fpga. ESP32 was the slave. highly reliable, tested upto 10MHz and 512 bits for transaction length

A Custom AXI4 SPI Peripheral

FPGA Digital Hardware Design

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

Customizable multi chip select supporting Serial Peripheral Interface master.

SPI protocol in VHDL

SPI master and SPI slave for FPGA written in VHDL

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

Various projects of SPI loader module for xilinx fpga