lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Simple single-port AXI memory interface
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Common SystemVerilog components
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
VeeR EL2 Core
[UNRELEASED] FP div/sqrt unit for transprecision
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISC-V Debug Support for our PULP RISC-V Cores