YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
RTL, Cmodel, and testbench for NVDLA
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
An Open-source FPGA IP Generator
NeoGeo for MiSTer
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects