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Language: Verilog
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analogdevicesinc / hdl
HDL libraries and projects
YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
EttusResearch / uhd
The USRP™ Hardware Driver Repository
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation