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ISLPED 2010: Austin, Texas, USA
- Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim:
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, ISBN 978-1-4503-0146-6
Alternative memory and emerging devices
- Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. 1-6 - Hamed F. Dadgour, Muhammad Mustafa Hussain
, Kaustav Banerjee:
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. 7-12 - Subho Chatterjee, Sayeef S. Salahuddin, Satish Kumar, Saibal Mukhopadhyay:
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. 13-18 - Wei Zhang, Ki Chul Chun, Chris H. Kim:
Variation aware performance analysis of gain cell embedded DRAMs. 19-24 - Dimin Niu, Yiran Chen, Yuan Xie:
Low-power dual-element memristor based memory design. 25-30
Variation-aware and reconfigurable design
- Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun:
Power-efficient variation-aware photonic on-chip network management. 31-36 - Somnath Paul, Swarup Bhunia
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. 37-42 - Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnappa, Prasad Shabadi, Wayne P. Burleson:
Low-power sub-threshold design of secure physical unclonable functions. 43-48 - Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum:
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. 49-54 - Yibo Chen, Jishen Zhao, Yuan Xie:
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. 55-60
Microarchitectures and scheduling
- Marshnil Vipin Dave, Rajkumar Satkuri, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
Low-power current-mode transceiver for on-chip bidirectional buses. 61-66 - Nadav Levison, Shlomo Weiss:
Low power branch prediction for embedded application processors. 67-72 - Alyssa Bonnoit, Lawrence T. Pileggi:
Reducing variability in chip-multiprocessors with adaptive body biasing. 73-78 - Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chaitali Chakrabarti, Scott A. Mahlke, Trevor N. Mudge:
Diet SODA: a power-efficient processor for digital cameras. 79-84 - Weixun Wang, Xiaoke Qin, Prabhat Mishra
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. 85-90
Low-power design for scaled low-voltage processes
- Rajeev K. Dokania, Xiao Y. Wang, Carlos I. Dorta-Quinones, Waclaw Godycki, Siddharth G. Tallur
A 6µw, 100kbps, 3-5ghz, UWB impulse radio transmitter. 91-94 - Leila Koushaeian, Stan Skafidas
A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp. 95-98 - Chien-Chun Lu, Ming-Ching Kuo:
A 5V output voltage boost switching converter with hybrid digital and analog PWM control. 99-104 - Amir Zjajo, Mingxin Song:
A low-power digitally-programmable variable gain amplifier in 65 nm CMOS. 105-110
Poster session
- Vinayak Honkote, Baris Taskin:
PEEC based parasitic modeling for power analysis on custom rotary rings. 111-116 - Georgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy:
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs. 117-122 - Qiang Gao, Yin Shen, Yici Cai, Hailong Yao:
Analog circuit shielding routing algorithm based on net classification. 123-128 - Shrikanth Ganapathy, Ramon Canal, Antonio González
MODEST: a model for energy estimation under spatio-temporal variability. 129-134 - Hyunhee Kim, Jung Ho Ahn, Jihong Kim:
Replication-aware leakage management in chip multiprocessors with private L2 cache. 135-140 - Hai Lin, Yunsi Fei
Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives. 141-146 - Dursun Baran
Energy efficient implementation of parallel CMOS multipliers with improved compressors. 147-152 - Jian (Denny) Lin, Wei Song, Albert Mo Kim Cheng
Real-energy: a new framework and a case study to evaluate power-aware real-time scheduling algorithms. 153-158 - Martin Saint-Laurent, Animesh Datta:
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. 159-164 - Bing Shi, Yufu Zhang, Ankur Srivastava
Dynamic thermal management for single and multicore processors under soft thermal constraints. 165-170 - Rahul Singh, AhReum Kim, SoYoung Kim, Suhwan Kim:
A three-step power-gating turn-on technique for controlling ground bounce noise. 171-176 - S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay:
Customizing pattern set for test power reduction via improved X-identification and reordering. 177-182 - Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
Analysis and design of ultra low power thermoelectric energy harvesting systems. 183-188 - Howard David, Eugene Gorbatov, Ulf R. Hanebutte, Rahul Khanna, Christian Le:
RAPL: memory power estimation and capping. 189-194 - Raid Zuhair Ayoub, Krishnam Raju Indukuri, Tajana Simunic Rosing:
Energy efficient proactive thermal management in memory subsystem. 195-200 - Karthick Rajamani, Freeman L. Rawson III, Malcolm S. Ware, Heather Hanson, John B. Carter, Todd J. Rosedahl, Andrew J. Geissler, Guillermo J. Silva, Hong Hua:
Power-performance management on an IBM POWER7 server. 201-206 - Domenic Forte
Energy and thermal-aware video coding via encoder/decoder workload balancing. 207-212 - Jibang Liu, Karthik Kumar, Yung-Hsiang Lu:
Tradeoff between energy savings and privacy protection in computation offloading. 213-218 - Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. 219-224 - Jungseob Lee, Chi-Chao Wang, Hamid Reza Ghasemi, Lloyd Bircher, Yu Cao
Workload-adaptive process tuning strategy for power-efficient multi-core processors. 225-230 - Tae-Hwan Kim, In-Cheol Park:
Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. 231-236
Keynote address
- Ajith Amerasekera:
Ultra low power electronics in the next decade. 237-238 - Kevin J. Nowka
Technology variability and uncertainty implications for power- efficient VLSI systems. 239-240
Voltage scaling and adaptation for low-power
- Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu
Workload-aware neuromorphic design of low-power supply voltage controller. 241-246 - Jean-Michel Chabloz, Ahmed Hemani:
Distributed DVFS using rationally-related frequencies and discrete voltage levels. 247-252 - Mehmet Basoglu, Michael Orshansky, Mattan Erez:
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. 253-258 - Nandish Ashutosh Mehta
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. 259-264 - Alireza Vahdatpour, Miodrag Potkonjak:
Leakage minimization using self sensing and thermal management. 265-270 - Mingoo Seok, David T. Blaauw, Dennis Sylvester:
Clock network design for ultra-low power applications. 271-276
Analysis and optimization for energy-efficient systems
- Kun Li, Jie Wu, Yifei Jiang, Zyad Hassan, Qin Lv, Li Shang, Dragan Maksimovic:
Large-scale battery system modeling and analysis for emerging electric-drive vehicles. 277-282 - Ardalan Amiri Sani, Hasan Dumanli, Lin Zhong, Ashutosh Sabharwal:
Power-efficient directional wireless communication on small form-factor mobile devices. 283-288 - Sangyoung Park
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. 289-294 - Feng Chen, Xiaodong Zhang:
PS-BC: power-saving considerations in design of buffer caches serving heterogeneous storage devices. 295-300 - Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy:
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection. 301-306
Energy harvesting and power conversion systems
- Younghyun Kim
Maximum power transfer tracking for a photovoltaic-supercapacitor energy system. 307-312 - Chien-Ying Chen, Pai H. Chou:
DuraCap: a supercapacitor-based, power-bootstrapping, maximum power point tracking energy-harvesting system. 313-318 - David Meisner, Thomas F. Wenisch:
Peak power modeling for data center servers with switched-mode power supplies. 319-324 - Shaobo Liu, Jun Lu, Qing Wu, Qinru Qiu:
Load-matching adaptive task scheduling for energy efficiency in energy harvesting real-time embedded systems. 325-330
Thermal, variability, and reliability considerations in power-aware design
- Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda:
Post-silicon power characterization using thermal infrared emissions. 331-336 - Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. 337-342 - Andrea Calimera
Dynamic indexing: concurrent leakage and aging optimization for caches. 343-348
Special Session 1: energy-efficiency via error-resiliency
- Benjamin Vigoda, David Reynolds, Jeffrey Bernstein, Theophane Weber, Bill Bradley:
Low power logic for statistical inference. 349-354 - Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. 355-356 - Rakesh Kumar:
Computing with stochastic processors: revisiting the correctness contract between software and hardware. 357-358 - Ravi Nair:
Models for energy-efficient approximate computing. 359-360
Special session 2: energy storage systems for emerging applications
- Jeff Lee:
Battery management technology for an electric vehicle. 361-362 - Massoud Pedram, Naehyuck Chang, Younghyun Kim
Hybrid electrical energy storage systems. 363-368 - Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang:
Hybrid energy storage system integration for vehicles. 369-374
Embedded tutorial
- Mondira (Mandy) Deb Pant:
Microprocessor power delivery challenges in the Nano-Era. 375-376
Memory system design
- Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisan, Babak Falsafi:
TurboTag: lookup filtering to reduce coherence directory power. 377-382 - Ahmed M. Amin, Zeshan Chishti:
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. 383-388 - Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
An energy efficient cache design using spin torque transfer (STT) RAM. 389-394
Design optimization for low power
- Ashutosh Chakraborty, David Z. Pan:
PASAP: power aware structured ASIC placement. 395-400 - Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. 401-406 - Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten
A pareto-algebraic framework for signal power optimization in global routing. 407-412 - Seungwhun Paik, Sangmin Kim, Youngsoo Shin:
Wakeup synthesis and its buffered tree construction for power gating circuit designs. 413-418
Power analysis for high-performance microprocessor design techniques
- Jaehyun Park
Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors. 419-424 - Siddharth Garg, Diana Marculescu
Custom feedback control: enabling truly scalable on-chip power management for MPSoCs. 425-430 - Felipe Klein, Alexandro Baldassin
STM versus lock-based systems: an energy consumption perspective. 431-436 - Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen
Dynamic workload characterization for power efficient scheduling on CMP systems. 437-442
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