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ISSCC 2017: San Francisco, CA, USA
- 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. IEEE 2017, ISBN 978-1-5090-3758-2
- Laura Chizuko Fujino:
Reflections. 4 - Boris Murmann
:
Foreword: Intelligent Chips for a Smart World. 5 - Anantha P. Chandrakasan, Boris Murmann:
Session 1 overview: Plenary Session. 6-7 - Cliff Hou:
1.1 A smart design paradigm for smart chips. 8-13 - Ahmad Bahai:
1.2 Dynamics of exponentials in circuits and systems. 14-20 - Jonathan Rothberg:
1.3 The development of high-speed DNA sequencing: Jurassic Park, Neanderthal, Moore, and you. 23 - Lieven M. K. Vandersypen, Antoni van Leeuwenhoek:
1.4 Quantum computing - the next challenge in circuit and system design. 24-29 - Kohei Onizuka, Abbas Komijani, Piet Wambacq:
Session 2 overview: Power amplifiers. 30-31 - Song Hu, Fei Wang, Hua Wang
2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications. 32-33 - Debopriyo Chowdhury, Sraavan R. Mundlapudi, Ali Afsahi:
2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology. 34-35 - Shang-Hsien Yang, Yen-Ting Lin, Yu-Sheng Ma, Hung-Wei Chen, Ke-Horng Chen
2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator. 36-37 - Xun Liu, Heng Zhang, Min Zhao, Xuan Chen, Philip K. T. Mok, Howard C. Luong:
2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA. 38-39 - Jenwei Ko, Xiaochuan Guo, Changhua Cao, Saravanan Rajapandian, Solti Peng, Jing Li, Wenchang Lee, Narayanan Baskaran, Caiyi Wang:
2.5 A high-efficiency multiband Class-F power amplifier in 0.153µm bulk CMOS for WCDMA/LTE applications. 40-41 - Junlei Zhao, Elham Rahimi, Francesco Svelto, Andrea Mazzanti:
2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage. 42-43 - Sherif Shakib, Mohamed Elkholy, Jeremy Dunworth
2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS. 44-45 - Voravit Vorapipat, Cooper S. Levy, Peter M. Asbeck:
2.8 A Class-G voltage-mode Doherty power amplifier. 46-47 - Thomas Burd, James Myers, Byeong-Gyu Nam:
Session 3 overview: Digital processors. 48-49 - Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. 50-51 - Teja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co:
3.2 Zen: A next-generation high-performance ×86 core. 52-53 - David Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration. 54-55 - Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. 56-57 - Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo:
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. 58-59 - Hemanth Prabhu, Joachim Neves Rodrigues, Liang Liu
3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI. 60-61 - Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. 62-63 - Hayato Wakabayashi, Jun Deguchi, Makoto Ikeda:
Session 4 overview: Imagers. 64-65 - Bongki Son
4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation. 66-67 - Arjang Hassibi, Rituraj Singh, Arun Manickam, Ruma Sinha, Bob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten A. Johnson, Mark W. McDermott, Nicholas Wood, Piyush Savalia, Nader Gamini:
4.2 A fully integrated CMOS fluorescence biochip for multiplex polymerase chain-reaction (PCR) processes. 68-69 - Min-Woong Seo, Yuya Shirakawa, Yuriko Masuda, Yoshimasa Kawata, Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito:
4.3 A programmable sub-nanosecond time-gated 4-tap lock-in pixel CMOS image sensor for real-time fluorescence lifetime imaging microscopy. 70-71 - Wootaek Lim, Dennis Sylvester, David T. Blaauw:
4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiode. 72-73 - Masahiro Kobayashi
4.5 A 1.8erms- temporal noise over 110dB dynamic range 3.4µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers, SS-ADC and multiple-accumulation shutter. 74-75 - Tsutomu Haruta, Tsutomu Nakajima, Jun Hashizume, Taku Umebayashi, Hiroshi Takahashi, Kazuo Taniguchi, Masami Kuroda, Hiroshi Sumihiro, Koji Enoki
4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM. 76-77 - Shin'ichi Machida
4.7 A 2.1Mpixel organic-film stacked RGB-IR image sensor with electrically controllable IR sensitivity. 78-79 - Min-Woong Seo, Tongxi Wang, Sung-Wook Jun, Tomoyuki Akahori, Shoji Kawahito:
4.8 A 0.44e-rms read-noise 32fps 0.5Mpixel high-sensitivity RG-less-pixel CMOS image sensor using bootstrapping reset. 80-81 - Tomohiro Yamazaki, Hironobu Katayama, Shuji Uehara, Atsushi Nose, Masatsugu Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, Shizunori Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Yoshinori Muramatsu, Masatoshi Ishikawa
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing. 82-83 - Tim Piessens, Vadim Ivanov, Axel Thomsen:
Session 5 overview: Analog techniques. 84-85 - Fred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink:
5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter. 86-87 - Ji-Hun Lee
5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWM. 88-89 - Ming Ding, Yao-Hong Liu
5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load. 90-91 - Karthik Pappu, George Pieter Reitsma, Sumant Bapat:
5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency counting. 92-93 - Jahyun Koo, Kyoung-Sik Moon, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop. 94-95 - Anand Savanth
5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability. 96-97 - Hanqing Wang, Gerard Mora-Puchalt, Colin Lyden, Roberto Maurino, Christian Birk:
5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability. 98-99 - Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son
5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. 100-101 - Ying-Chih Hsu, Chia-Liang Tai, Mei-Chen Chuang, Alan Roth, Eric G. Soenen:
5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm2 area. 102-103 - Weiwei Xu, Prasanna Upadhyaya, Xiaoyue Wang, Randy Tsang, Li Lin:
5.10 A 1A LDO regulator driven by a 0.0013mm2 Class-D controller. 104-105 - Fan Yang
5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over -20dB PSR at 0.2V lowest supply voltage. 106-107 - Simone Erba, Takayuki Shibasaki, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline. 108-109 - Pen-Jui Peng
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS. 110-111 - Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon:
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. 112-113 - Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang:
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. 114-115 - Giovanni Steffan, Emanuele Depaoli, Enrico Monaco, Nicolo Sabatino, Walter Audoglio, Augusto Andrea Rossi, Simone Erba, Matteo Bassi, Andrea Mazzanti:
6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI. 116-117 - Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli:
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. 118-119 - Wahid Rahman
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. 120-121 - Joshua Liang
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. 122-123 - Yuu Watanabe, Danielle Griffith, Aarno Pärssinen:
Session 7 overview: Wireless transceivers. 124-125 - Tsung-Ming Chen, Yi Lu, Pang-Ning Chen, Yu-Hsien Chang, Ming-Chung Liu, Po-Yu Chang, Chia-Jen Liang, Yi-Chu Chen, Hsi-Liang Lu, Jian-Yu Ding, Chin-Chung Wang, YuLi Hsueh, Jen-Che Tsai, Min-Shun Hsu, Yuan-Hung Chung, George Chien:
7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate. 126-127 - Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia:
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication. 128-129 - Chinq-Shiun Chiu, Shih-Chieh Yen, Chi-Yao Yu, Tzung-Han Wu, Chung-Yun Chou, Sheng-Che Tseng, Chih-Hsien Shen, Yu-Tsung Lu, Hsinhung Chen, Song-Yu Yang, Yen-Tso Chen, Guang-Kaai Dehng, Yangjian Chen, Christophe Beghein, Dimitris Nalbantis, Manel Collados, Bernard Tenbroek, Jonathan Strange, Caiyi Wang:
7.3 A 40nm low-power transceiver for LTE-A Carrier Aggregation. 130-131 - Li-Xuan Chuo, Yao Shi, Zhihong Luo, Nikolaos Chiotellis, Zhiyoong Foo, Gyouho Kim, Yejoong Kim
7.4 A 915MHz asymmetric radio using Q-enhanced amplifier for a fully integrated 3×3×3mm3 wireless sensor node with 20m non-line-of-sight communication. 132-133 - David Lachartre, Francois Dehmas
7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks. 134-135 - Wei Yang, De Yong Hu, Chun Kit Lam, Ji Qing Cui, Lip Kai Soh, De-Cheng Song, Xiao Wei Zhong, Hon Cheong Hor, Chee Lee Heng:
7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and -58dBc TX HD2. 136-137 - Nikolaj Andersen
7.7 A 118mW 23.3GS/s dual-band 7.3GHz and 8.7GHz impulse-based direct RF sampling radar SoC in 55nm CMOS. 138-139 - Yasuhisa Shimazaki, John Maneatis, Edith Beigné:
Session 8 overview: Digital PLLs and security circuits. 140-141 - Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. 142-143 - Eunhwan Kim, Minah Lee
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors. 144-145 - Kaiyuan Yang
8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability. 146-147 - Tae-Kwang Jang
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. 148-149 - Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. 150-151 - Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. 152-153 - Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. 154-155 - Pedram Lajevardi, Masayuki Miyamoto, Makoto Ikeda:
Session 9 overview: Sensors. 156-157 - Sining Pan, Yanquan Luo, Saleh Heidary Shalmany, Kofi A. A. Makinwa:
9.1 A resistor-based temperature sensor with a 0.13pJ·K2 resolution FOM. 158-159 - Kaiyuan Yang
9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence. 160-161 - Bahman Yousefzadeh, Kofi A. A. Makinwa:
9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from -55°C to +125°C after heater-assisted voltage calibration. 162-163 - Maximilian Marx
9.4 A 27µW 0.06mm2 background resonance frequency tuning circuit based on noise observation for a 1.71mW CT-ΔΣ MEMS gyroscope readout system with 0.9°/h bias instability. 164-165 - Elmar Bach, Richard Gaggl
9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR. 166-167 - Jae-Sung An, Sang-Hyun Han, Ju Eon Kim, Dong-Hyun Yoon, Young-Hwan Kim, Han-Hee Hong, Jae-Hun Ye, Sung-Jin Jung, Seung-Hwan Lee, Ji-Yong Jeong, Kwang-Hyun Baek, Seong-Kwan Hong, Oh-Kyong Kwon:
9.6 A 3.9kHz-frame-rate capacitive touch system with pressure/tilt angle expressions of active stylus using multiple-frequency driving method for 65″ 104×64 touch screen panel. 168-169 - Hyunseok Hwang, Hyeyeon Lee, Hongchae Kim, Youngcheol Chae:
9.7 A 6.9mW 120fps 28×50 capacitive touch sensor with 41.7dB SNR for 1mm stylus using current-driven ΔΣ ADCs. 170-171 - Hui Jiang
9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme. 172-173 - Vikram Chaturvedi, Mohammad Reza Nabavi, Johan Vogel, Kofi A. A. Makinwa, Stoyan N. Nihtianov:
9.9 A 0.6nm resolution 19.8mW eddy-current displacement sensor interface with 126MHz excitation. 174-175 - Hoi Lee, Gerard Villar Pique, Axel Thomsen:
Session 10 overview: DC-DC converters. 176-177 - Nicolas Butzen, Michiel Steyaert
10.1 A 1.1W/mm2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging. 178-179 - Christopher Schaef, Eric Din, Jason T. Stauth
10.2 A digitally controlled 94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery arrays. 180-181 - Wen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski:
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS. 182-183 - Yong-Min Ju, Se-un Shin, Yeunhee Huh, Sang-Hui Park, Jun-Suk Bang, Kiduk Kim, Sung-Won Choi, Ji-Hun Lee
10.4 A hybrid inductor-based flying-capacitor-assisted step-up/step-down DC-DC converter with 96.56% efficiency. 184-185 - Li-Cheng Chu, Wen-Hau Yang, Xiao-Qing Zhang, Yan-Jiun Lai, Ke-Horng Chen
10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response. 186-187 - Lin Cheng, Wing-Hung Ki
10.6 A 30MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transient. 188-189 - Bumkil Lee, Min Kyu Song, Ashis Maity
10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range. 190-191 - Arun Paidimarri, Anantha P. Chandrakasan:
10.8 A Buck converter with 240pW quiescent power, 92% peak efficiency and a 2×106 dynamic range. 192-193 - Takashi Kono, Ki-Tae Park, Leland Chang:
Session 11 overview: Nonvolatile memory solutions. 194-195 - Ryuji Yamashita, Sagar Magia, Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura, Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, Hardwell Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, Takuyo Kodama, Yoshihiko Kamata, Yuzuru Namai, Jonathan Huynh, Sung-En Wang, Yankang He, Trung Pham, Vivek Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, Hitoshi Miwa, Aditya Pradhan, Sulagna Dey, Debasish Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, Gopinath Balakrishnan, Takuya Ariki, Kapil Verma, Chang Hua Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, Farookh Moogat:
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. 196-197 - Qing Dong, Yejoong Kim
11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes. 198-199 - Shau-Yu Chou, Yu-Shiang Chen, Jun-Hao Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme. 200-201 - Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, Il-Han Park, Hyun Wook Park, Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jong-Hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, Byunghoon Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sunghoon Kim, Dongkyu Yoon, Ki-Sung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-Yub Lee, Ki-Tae Park, Kyehyun Kyung:
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory. 202-203 - Fatih Hamzaoglu, Chun Shiah, Leland Chang:
Session 12 overview: SRAM. 204-205 - Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu:
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. 206-207 - Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. 208-209 - Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang:
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. 210-211 - Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns:
12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. 212-213 - Guang-Kaai Dehng, Kyoohyun Lim, Aarno Pärssinen:
Session 13 overview: High-performance transmitters. 214-215 - Ming-Da Tsai, Chien-Cheng Lin, Ping-Yu Chen, Tao-Yao Chang, Chien-Wei Tseng, Lai-Ching Lin, Chris Beale, Bosen Tseng, Bernard Tenbroek, Chinq-Shiun Chiu, Guang-Kaai Dehng, George Chien:
13.1 A fully integrated multimode front-end module for GSM/EDGE/TD-SCDMA/TD-LTE applications using a Class-F CMOS power amplifier. 216-217 - Michael Fulde, Alexander Belitzer, Zdravko Boos, Michael Bruennert, Jonas Fritzin, Hans Geltinger, Marcus Groinig, Daniel Gruber
13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS. 218-219 - Venumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang Won Son:
13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. 220-221 - Enrico Roverato, Marko Kosunen
13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping. 222-223 - Marko Kosunen
13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth. 224-225 - Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas:
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. 226-227 - David Cousinard, Renaldi Winoto, Hao Li, Yuan Fang, Amir Ghaffari, Ashkan Olyaei, Ovidiu Carnu, Philip Godoy, Alden Wong, Xingliang Zhao, Jiexi Liu, Arnab Mitra, Randy Tsang, Li Lin:
13.7 A 0.23mm2 digital power amplifier with hybrid time/amplitude control achieving 22.5dBm at 28% PAE for 802.11g. 228-229 - Jong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull, Hua Wang
13.8 A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensation. 230-231 - Antonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE. 232-233 - Ritesh Bhat, Jin Zhou, Harish Krishnaswamy:
13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor. 234-235 - Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam:
Session 14 overview: Deep-learning processors. 236-237 - Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Surinder Pal Singh, Elio Guidetti, Fabio De Ambroggi, Tommaso Majo, Paolo Zambotti, Manuj Ayodhyawasi, Harvinder Singh, Nalin Aggarwal:
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems. 238-239 - Dongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo:
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks. 240-241 - Paul N. Whatmough, Sae Kyu Lee, Hyunkwang Lee, Saketh Rama, David M. Brooks, Gu-Yeon Wei:
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications. 242-243 - Michael Price, James R. Glass, Anantha P. Chandrakasan:
14.4 A scalable speech recognizer with deep-neural-network acoustic models and voice-activated power gating. 244-245 - Bert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI. 246-247 - Kyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Sanghoon Kang, Youchang Kim, Hoi-Jun Yoo:
14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector. 248-249 - Suyoung Bang, Jingcheng Wang, Ziyun Li, Cao Gao, Yejoong Kim
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. 250-251 - Yi-Chung Wu
14.8 A 135mW fully integrated data processor for next-generation sequencing. 252-253 - Jan Genoe
Session 15 overview: Innovations in technologies and circuits. 254-255 - Yasmin Afsar, Tiffany Moy, Nicholas Brady, Sigurd Wagner, James C. Sturm, Naveen Verma:
15.1 Large-scale acquisition of large-area sensors using an array of frequency-hopping ZnO thin-film-transistor oscillators. 256-257 - Kris Myny
15.2 A flexible ISO14443-A compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier. 258-259 - Carmine Garripoli, Jan-Laurens P. J. van der Steen, Edsger C. P. Smits, Gerwin H. Gelinck, Arthur H. M. van Roermund, Eugenio Cantatore:
15.3 An a-IGZO asynchronous delta-sigma modulator on foil achieving up to 43dB SNR and 40dB SNDR in 300Hz bandwidth. 260-261 - SungWon Chung, Hooman Abediasl, Hossein Hashemi
15.4 A 1024-element scalable optical phased array in 0.18µm SOI CMOS. 262-263 - Edoardo Charbon, Fabio Sebastiano
15.5 Cryo-CMOS circuits and systems for scalable quantum computing. 264-265 - Guillaume Gourlat, Marc Sansa
15.6 A 30-to-80MHz simultaneous dual-mode heterodyne oscillator targeting NEMS array gravimetric sensing applications with a 300zg mass resolution. 266-267 - Bayan Nasri
15.7 Heterogeneous integrated CMOS-graphene sensor array for dopamine detection. 268-269 - Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure. 270-271 - Xuyang Lu, Lingyu Hong, Kaushik Sengupta
15.9 An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS. 272-273 - Jan Mulder, Paul Ferguson, Un-Ku Moon:
Session 16 overview: Gigahertz data converters. 274-275 - Bruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley:
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. 276-277 - Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson:
16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD. 278-279 - Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi, Bob Verbruggen, John McGrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley:
16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz. 280-281 - Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. 282-283 - John P. Keane, Nathaniel J. Guilar, Dusan Stepanovic, Bernd Wuppermann, Charles Wu, Cheongyuen W. Tsang, Robert Neff, Ken Nishimura:
16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOS. 284-285 - Lucas Duncan, Brian Dupaix, Jamin J. McCue, Brandon Mathieu, Matthew LaRue, Mesfin Teshome, Myung-Jun Choe, Waleed Khalil:
16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR. 286-287 - Siddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. 288-289 - Brian P. Ginsburg, Payam Heydari, Piet Wambacq:
Session 17 overview: TX and RX building blocks. 290-291 - Yuen-Hui Chee, Fatih Golcuk, Toru Matsuura, Christopher Beale, James F. Wang, Osama Shana'a
17.1 A digitally assisted CMOS WiFi 802.11ac/11ax front-end module achieving 12% PA efficiency at 20dBm output power with 160MHz 256-QAM OFDM signal. 292-293 - Tolga Dinc, Harish Krishnaswamy:
17.2 A 28GHz magnetic-free non-reciprocal passive CMOS circulator based on spatio-temporal conductance modulation. 294-295 - Taiyun Chi, Fei Wang, Sensen Li, Min-Yu Huang, Jong Seok Park, Hua Wang
17.3 A 60GHz on-chip linear radiator with single-element 27.9dBm Psat and 33.1dBm peak EIRP using multifeed antenna for direct on-antenna power combining. 296-297 - Chuang Lu, Ao Ba, Yao-Hong Liu
17.4 A sub-mW antenna-impedance detection using electrical balance for single-step on-chip tunable matching in wearable/implantable applications. 298-299 - Mohsen Hashemi, Yiyu Shen, Mohammadreza Mehrpoo, Mustafa Acar, Rene van Leuken, Morteza S. Alavi
17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking. 300-301 - Cheng Wang, Ruonan Han:
17.6 Rapid and energy-efficient molecular sensing using dual mm-Wave combs in 65nm CMOS: A 220-to-320GHz spectrometer with 5.2mW radiated power and 14.6-to-19.5dB noise figure. 302-303 - Taiyun Chi, Min-Yu Huang, Sensen Li, Hua Wang
17.7 A packaged 90-to-300GHz transmitter and 115-to-325GHz coherent receiver in CMOS for full-band continuous-wave mm-wave hyperspectral imaging. 304-305 - Nemat Dolatsha, Baptiste Grave, Mahmoud Sawaby, Cheng Chen
17.8 A compact 130GHz fully packaged point-to-point wireless system with 3D-printed 26dBi lens antenna achieving 12.5Gb/s at 1.55pJ/b/m. 306-307 - Kyoya Takano
17.9 A 105Gb/s 300GHz CMOS transmitter. 308-309 - Hossein Jalili
17.10 A 318-to-370GHz standing-wave 2D phased array in 0.13µm BiCMOS. 310-311 - Alyosha C. Molnar, Jan Craninckx, Aarno Pärssinen:
Session 18 overview: Full duplex wireless front-ends. 312-313 - Tong Zhang, Ali Najafi, Chenxin Su, Jacques Christophe Rudell:
18.1 A 1.7-to-2.2GHz full-duplex transceiver system with >50dB self-interference cancellation over 42MHz bandwidth. 314-315 - Negar Reiskarimian
18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wireless. 316-317 - Yu-Hsien Kao, Hao-Chung Chou, Chun-Chieh Peng, Yu-Jiu Wang, Borching Su, Ta-Shun Chu:
18.3 A single-port duplex RF front-end for X-band single-antenna FMCW radar in 65nm CMOS. 318-319 - Andrea Mazzanti, Xiang Gao, Piet Wambacq:
Session 19 overview: Frequency generation. 320-321 - Peyman Nazari, Saman Jafarlou, Payam Heydari:
19.1 A fundamental-frequency 114GHz circular-polarized radiating element with 14dBm EIRP, -99.3dBc/Hz phase-noise at 1MHz offset and 3.7% peak efficiency. 322-323 - Seyeon Yoo, Seojin Choi
19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. 324-325 - Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh:
19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter. 326-327 - Jeffrey Chuang, Harish Krishnaswamy:
19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOM. 328-329 - Long Kong, Behzad Razavi:
19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW. 330-331 - Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. 332-333 - Atsuki Inoue, Dennis Sylvester, Edith Beigné:
Session 20 overview: Digital voltage regulators and low-power techniques. 334-335 - Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De:
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. 336-337 - Wen-Jie Tsou, Wen-Hau Yang, Jian-He Lin, Hsin Chen, Ke-Horng Chen
20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. 338-339 - Loai G. Salem
20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V. 340-341 - Mo Huang
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. 342-343 - Junmin Jiang
20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. 344-345 - Doyun Kim, Jonghwan Kim, Hyunju Ham, Mingoo Seok:
20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor. 346-347 - Hsi-Shou Wu, Zhengya Zhang
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. 348-349 - Antoine Dupret, Pui-In Mak, Eugenio Cantatore:
Session 21 overview: Smart SoCs for innovative applications. 350-351 - Phillip M. Nadeau, Mark Mimee
21.1 Nanowatt circuit interface to whole-cell bacterial sensors. 352-353 - Minseo Kim
21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system. 354-355 - Hansraj Bhamra, Jui-Wei Tsai, Yu-Wen Huang, Quan Yuan, Pedro P. Irazoqui
21.3 A sub-mm3 wireless implantable intraocular pressure monitor microsystem. 356-357 - Xiaosen Liu, Adrian I. Colli-Menchi
21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels. 358-359 - Simon Chaput, David M. Brooks, Gu-Yeon Wei:
21.5 A 3-to-5V input 100Vpp output 57.7mW 0.42% THD+N highly integrated piezoelectric actuator driver. 360-361 - Seokhyeon Jeong, Yu Chen, Tae-Kwang Jang
21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification. 362-363 - Siddharth Joshi, Chul Kim, Sohmyung Ha
21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppression. 364-365 - Nachiket V. Desai, Chiraag Juvekar, Shubham Chandak
21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocation. 366-367 - Stefano Stanzione, Edgar Sánchez-Sinencio, Axel Thomsen:
Session 22 overview: Harvesting and wireless power. 368-369 - Henry Kennedy, Rares Bodnar, Teerasak Lee
22.1 A self-tuning resonant inductive link transmit driver using quadrature-symmetric phase-switched fractional capacitance. 370-371 - Zhiyuan Chen
22.2 A 1.7mm2 inductorless fully integrated flipping-capacitor rectifier (FCR) for piezoelectric energy harvesting with 483% power-extraction enhancement. 372-373 - Hesam Sadeghi Gougheri, Mehdi Kiani:
22.3 Adaptive reconfigurable voltage/current-mode power management with self-regulation for extended-range inductive power transmission. 374-375 - Mo Huang
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. 376-377 - Sandip Uprety, Hoi Lee:
22.5 A 93%-power-efficiency photovoltaic energy harvester with irradiance-aware auto-reconfigurable MPPT scheme achieving >95% MPPT efficiency across 650µW to 1W and 2.9ms FOCV MPPT transient time. 378-379 - Xiao Wu, Kyojin David Choo
22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems. 380-381 - Jiacheng Pan, Asad A. Abidi, Dejan Rozgic, Hariprasad Chandrakumar, Dejan Markovic:
22.7 An inductively-coupled wireless power-transfer system that is immune to distance and load variations. 382-383 - Yuan Gao
22.8 An AC-input inductorless LED driver for visible-light-communication applications with 8Mb/s data-rate and 6.4% low-frequency flicker. 384-385 - Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang:
Session 23 overview: DRAM, MRAM & DRAM interfaces. 386-387 - Martin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale:
23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications. 388-389 - Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon-Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-Young Oh, Indal Song, Yong-Cheol Bae, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. 390-391 - Nohhyup Kwak, Saeng-Hwan Kim, Kyong Ha Lee, Chang-Ki Baek, Mun Seon Jang, Yongsuk Joo, Seung-Hun Lee, Wooyoung Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung-Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications. 392-393 - Hye-Jung Kwon, Eunsung Seo
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. 394-395 - Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh:
23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. 396-397 - Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park:
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. 398-399 - Il-Min Yi
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. 400-401 - Woojun Choi, Taewoong Kim, Jongjoo Shim, Hyungsoo Kim, Gunhee Han, Youngcheol Chae:
23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. 402-403 - Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. 404-405 - Chun-Huat Heng, Ken Yamamoto, Aarno Pärssinen:
Session 24 overview: Wireless receivers and synthesizers. 406-407 - Yao-Hong Liu
24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications. 408-409 - Linxiao Zhang, Harish Krishnaswamy:
24.2 A 0.1-to-3.1GHz 4-element MIMO receiver array supporting analog/RF arbitrary spatial filtering. 410-411 - Yuanching Lien, Eric A. M. Klumperink, Bernard Tenbroek, Jon Strange, Bram Nauta
24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio. 412-413 - Wei-Han Yu
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. 414-415 - Haowei Jiang, Po-Han Peter Wang
24.5 A 4.5nW wake-up radio with -69dBm sensitivity. 416-417 - Sameed Hameed
24.6 A time-interleaved filtering-by-aliasing receiver front-end with >70dB suppression at <4× bandwidth frequency offset. 418-419 - Yuming He, Yao-Hong Liu
24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications. 420-421 - Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. 422-423 - Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. 424-425 - Shuichi Nagai, Yogesh K. Ramadass, Eugenio Cantatore:
Session 25 overview: GaN drivers and galvanic isolators. 426-427 - Lei Chen, Joseph Sankman, Rajarshi Mukhopadhyay, Mark Morgan, Dongsheng Brian Ma:
25.1 A 50.7% peak efficiency subharmonic resonant isolated capacitive power transfer system with 62mW output power for low-power industrial sensor interfaces. 428-429 - Xugang Ke, Joseph Sankman, Yingping Chen, Lenian He, Dongsheng Brian Ma:
25.2 A 10MHz 3-to-40V VIN tri-slope gate driving GaN DC-DC converter with 40.5dBµV spurious noise compression and 79.3% ringing suppression for automotive applications. 430-431 - Achim Seidel, Bernhard Wicht
25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storing. 432-433 - Subhashish Mukherjee, Anoop Narayan Bhat
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS. 434-435 - Kathy Wilcox, Youngmin Shin, Edith Beigné:
Session 26 overview: Processor-power management and clocking. 436-437 - Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran
26.2 Power supply noise in a 22nm z13™ microprocessor. 438-439 - Longyang Lin, Saurabh Jain, Massimo Alioto:
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage. 440-441 - Loai G. Salem, Patrick P. Mercier
26.4 A 0.4-to-1V 1MHz-to-2GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reduction. 442-443 - Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis:
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. 444-445 - Gert Cauwenberghs, Michiel A. P. Pertijs, Makoto Ikeda:
Session 27 overview: Biomedical circuits. 446-447 - Hariprasad Chandrakumar, Dejan Markovic:
27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVpp. 448-449 - Unsoo Ha, Jaehyuk Lee, Jihee Lee, Kwantae Kim
27.2 A 25.2mW EEG-NIRS multimodal SoC for accurate anesthesia depth monitoring. 450-451 - Hossein Kassiri, Reza Pazhouhandeh, Nima Soltani, Muhammad Tariqus Salam, Peter L. Carlen, José Luis Pérez Velazquez, Roman Genov:
27.3 All-wireless 64-channel 0.013mm2/ch closed-loop neurostimulator with rail-to-rail DC offset removal. 452-453 - Benjamin Sporrer, Lianbo Wu
27.4 A sub-1dB NF dual-channel on-coil CMOS receiver for Magnetic Resonance Imaging. 454-455 - Man-Chia Chen, Aldo Pena Perez, Sri-Rajasekhar Kothapalli, Philippe Cathelin, Andreia Cathelin, Sanjiv Sam Gambhir, Boris Murmann
27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI. 456-457 - Yusaku Katsube, Shinya Kajiyama, Takuma Nishimoto, Tatsuo Nakagawa, Yasuyuki Okuma, Yohei Nakamura, Takahide Terada, Yutaka Igarashi, Taizo Yamawaki, Toru Yazaki, Yoshihiro Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka:
27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging. 458-459 - Ting Chia Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, Amin Arbabian:
27.7 A 30.5mm3 fully packaged implantable device with duplex ultrasonic data and power links achieving 95kb/s with <10-4 BER at 8.5cm depth. 460-461 - Lingyu Hong, Kaushik Sengupta
27.8 Fully integrated optical spectrometer with 500-to-830nm range in 65nm CMOS. 462-463 - Tai-Cheng Lee, Bob Verbruggen, Un-Ku Moon:
Session 28 overview: Hybrid ADCs. 464-465 - Chun-Cheng Liu, Mu-Chen Huang:
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter. 466-467 - Taewook Kim, Changsok Han, Nima Maghari:
28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizer. 468-469 - Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn:
28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS. 470-471 - Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu
28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. 472-473 - Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. 474-475 - Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS. 476-477 - Kentaro Yoshioka
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. 478-479 - Samuel Palermo, Hideyuki Nosaka, Frank O'Mahony:
Session 29 overview: Optical- and electrical-link innovations. 480-481 - Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. 482-483 - Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz:
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS. 484-485 - Sajjad Moazeni, Sen Lin, Mark T. Wade, Luca Alloatti, Rajeev J. Ram, Milos A. Popovic
29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS. 486-487 - Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand:
29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS. 488-489 - Yeonho Lee, Yoonjae Choi
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. 490-491 - Romesh Kumar Nandwana, Saurabh Saxena
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. 492-493 - Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. 494-495 - Ali Sheikholeslami:
Tutorials. 498-499 - Makoto Takamiya, Yogesh K. Ramadass, Keith A. Bowman, Gerard Villar Pique, Shuichi Nagai, Dennis Sylvester:
F1: Integrated voltage regulators for SoC and emerging IoT systems. 500-502 - Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. 503-505 - Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst:
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. 506-508 - Jan van Sinderen, Danielle Griffith, Ken Yamamoto, Antonio Liscidini, Young-sub Yuk:
F4: Wireless low-power transceivers for local and wide-area networks. 509-511 - Yohan Frans, Ichiro Fujimori, Seung-Jun Bae, Samuel Palermo, Hideyuki Nosaka, Simone Erba:
F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. 512-514 - Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U:
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. 515-517 - SeongHwan Cho, Denis Daly:
EE1: Student Research Preview. 518-520 - Stefano Pellerano, Sungdae Choi, Jan M. Rabaey:
EE2: Intelligent machines: Will the technological singularity happen? 521 - Edoardo Charbon:
EE3: Quantum engineering: Hype, spin or reality? 522 - Ichiro Fujimori, Pavan Kumar Hanumolu:
EE4: Semiconductor economics: How business decisions are engineered. 523 - Martin Brox, Jonathan Chang, Howard C. Luong, Paul Liang, Riccardo Mariani:
EE5: When will we stop driving our cars? 524 - Harry Lee, Matt Straayer, Chris Mangelsdorf:
EE6: Return of survey says! 525 - Daniel J. Friedman:
Ultra-low-power analog design. 526-527
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