default search action
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 40
Volume 40, Number 1, January 2021
- Minho Ha
, Younghoon Byun
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network. 1-10 - Kyle Juretus
Synthesis of Hidden State Transitions for Sequential Logic Locking. 11-23 - Boyou Zhou
Hardware Trojan Detection Using Backside Optical Imaging. 24-37 - Kyle Juretus
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking. 38-51 - Jinhua Cui
SmartHeating: On the Performance and Lifetime Improvement of Self-Healing SSDs. 52-65 - Weihua Liu
DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD. 66-77 - Yiwen Zhang
Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm. 78-86 - Sung-Ming Wu
Integrating LSM Trees With Multichip Flash Translation Layer for Write-Efficient KVSSDs. 87-100 - Zhehui Wang
Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition. 101-114 - Chunfeng Liu, Xing Huang
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. 115-128 - Zhuoran Song
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. 129-142 - Mohammed Shayan
How Secure Are Checkpoint-Based Defenses in Digital Microfluidic Biochips? 143-156 - Dimitrios Baxevanakis
A General Time-Domain Method for Harmonic Distortion Estimation in CMOS Circuits. 157-170 - Jingwen Leng
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs. 171-184 - Zhanwei Zhong
Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism. 185-198 - Wenfei Zhang, Yaoyao Ye
A Table-Free Approximate Q-Learning-Based Thermal-Aware Adaptive Routing for Optical NoCs. 199-203
Volume 40, Number 2, February 2021
- Xinmi Yang
An Efficient Analysis Method for LTCC Ridge Waveguide Bandpass Filters via Database Searching. 205-217 - Shuo-Han Chen
Optimizing Lifetime Capacity and Read Performance of Bit-Alterable 3-D NAND Flash. 218-231 - Quan Zhou
Limited Busy Periods in Response Time Analysis for Tasks Under Global EDF Scheduling. 232-245 - Zirui Xu
DiReCtX: Dynamic Resource-Aware CNN Reconfiguration Framework for Real-Time Mobile Applications. 246-259 - Mengquan Li
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip. 260-273 - Hao Zhang, Ke Liu
Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs. 274-286 - Yuhang Zhang
Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel. 287-300 - Junnan Shan
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms. 301-314 - Amr G. Wassal, Ahmed M. Ibrahim
Multistage Multirate Transfer Function Automated Synthesis Using Hybrid Sampling Strategy-Based Differential Evolution. 315-325 - Shubham Jain
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. 326-338 - Gerold Fink
Automatic Design of Droplet-Based Microfluidic Ring Networks. 339-349 - Liang Chen
A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects. 350-363 - John Vista
Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation. 364-372 - Mohamed Baker Alawieh
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. 373-385 - Renjian Pan, Zhaobo Zhang, Xin Li, Krishnendu Chakrabarty
Black-Box Test-Cost Reduction Based on Bayesian Network Models. 386-399 - Yun-Jhe Jiang, Kuo-Hao Wu, Shao-Yun Fang
Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials. 400-404
Volume 40, Number 3, March 2021
- Aysha S. Shanta
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications. 405-418 - Ali Hoseinghorban
CHANCE: Capacitor Charging Management Scheme in Energy Harvesting Systems. 419-429 - Shunzhuo Wang
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs. 430-443 - Tim Daulby
Improving the Forward Progress of Transient Systems. 444-452 - Yuting Dai
Toward Efficient Execution of Mainstream Deep Learning Frameworks on Mobile Devices: Architectural Implications. 453-466 - Umberto Garlando
FUNCODE: Effective Device-to-System Analysis of Field-Coupled Nanocomputing Circuit Designs. 467-478 - Yehya Nasser
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey. 479-493 - Yu-Chen Liao
Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os. 494-506 - Xiaoyi Wang
Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution. 507-520 - Chaoxun Pan, Qinghui Hong
A Novel Memristive Chaotic Neuron Circuit and Its Application in Chaotic Neural Networks for Associative Memory. 521-532 - Chen-Hao Hsu
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. 533-546 - Andrew B. Kahng, Lutong Wang
TritonRoute: The Open-Source Detailed Router. 547-559 - Jianli Chen, Yao-Wen Chang, Yu-Chen Huang:
Analytical Placement Considering the Electron-Beam Fogging Effect. 560-573 - Hongyu An
Robust Deep Reservoir Computing Through Reliable Memristor With Improved Heat Dissipation Capability. 574-583 - Friedrich Hapke
Defect-Oriented Test: Effectiveness in High Volume Manufacturing. 584-597 - Irith Pomeranz
Maximal Independent Fault Set for Gate-Exhaustive Faults. 598-602 - Junzhe Cai
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. 603-607
Volume 40, Number 4, April 2021
- Abhishek Chakraborty
Evaluating the Security of Delay-Locked Circuits. 608-619 - Changhai Ou
SNR-Centric Power Trace Extractors for Side-Channel Attacks. 620-632 - Khushboo Rani
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon. 633-645 - Javad Saber-Latibari
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems. 646-654 - Naoya Onizawa
A Design Framework for Invertible Logic. 655-665 - Wentai Zhang
FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction. 666-679 - Mathieu Dumont, Mathieu Lisart, Philippe Maurine
Modeling and Simulating Electromagnetic Fault Injection. 680-693 - Sheriff Sadiqbatcha
Post-Silicon Heat-Source Identification and Machine-Learning-Based Thermal Modeling Using Infrared Thermal Imaging. 694-707 - Konstantin O. Petrosyants
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From -200 °C to +300 °C). 708-722 - O. V. S. Shashank Ram
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning. 723-734 - He-Teng Zhang
SAT-Based On-Track Bus Routing. 735-747 - Yibo Lin
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. 748-761 - Chengning Wang
Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory. 762-775 - Tsung-Wei Huang
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine. 776-789 - Yu-Hsiang Chen
Test Chips With Scan-Based Logic Arrays. 790-802 - Irith Pomeranz
PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests. 803-807
Volume 40, Number 5, May 2021
- Weidong Cao
Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM. 808-821 - Julian Leonhard, Alhassan Sayed
Analog and Mixed-Signal IC Security via Sizing Camouflaging. 822-835 - Baogang Zhang
Computational Restructuring: Rethinking Image Compression Using Resistive Crossbar Arrays. 836-849 - Sai Vineel Reddy Chittamuru
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks. 850-863 - Feng Wang
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. 864-877 - Xinyuan Qu
Cheetah: An Accurate Assessment Mechanism and a High-Throughput Acceleration Architecture Oriented Toward Resource Efficiency. 878-891 - Gyoung-Hwan Hyun, Taewhan Kim
Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach. 892-903 - Nian-Ze Lee
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits. 904-917 - Ying Wang
An Edge 3D CNN Accelerator for Low-Power Activity Recognition. 918-930 - Jingjing Guo
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. 931-944 - Jin-Tai Yan
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits. 945-956 - Hao-Chiang Shao
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach. 957-970 - Biresh Kumar Joardar
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture. 971-984 - V. S. Vineesh
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. 985-998 - Alvaro Cintas Canto
Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGA. 999-1003 - Irith Pomeranz
Padding of LFSR Seeds for Reduced Input Test Data Volume. 1004-1008
Volume 40, Number 6, June 2021
- Rajesh K. Gupta, David Atienza:
Editorial. 1009 - Wei Hu
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. 1010-1038 - Changhai Ou
The Science of Guessing in Collision-Optimized Divide-and-Conquer Attacks. 1039-1051 - Changhai Ou
Information Entropy-Based Leakage Profiling. 1052-1062 - Fan Zhang
Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level. 1063-1076 - Haocheng Ma
Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel Protection. 1077-1089 - Naman Singhal, Priyanka Joshi
Entropy Reduction Model for Pinpointing Differential Fault Analysis on SIMON and SIMECK Ciphers. 1090-1101 - Guorui Xu
Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers. 1102-1116 - Shihui Zheng
A Persistent Fault-Based Collision Analysis Against the Advanced Encryption Standard. 1117-1129 - Pengfei Qiu
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX. 1130-1143 - Fan Zhang
hPRESS: A Hardware-Enhanced Proxy Re-Encryption Scheme Using Secure Enclave. 1144-1157 - Benjamin Tan
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip. 1158-1171 - Peizhou Gan, Xiaojin Zhao
An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS. 1172-1182 - Chongyan Gu
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication. 1183-1196 - Pranesh Santikellur, Rajat Subhra Chakraborty
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants. 1197-1206 - Libang Zhang
Multilabel Deep Learning-Based Side-Channel Attack. 1207-1216 - Priyank Kashyap
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning. 1217-1229 - Xing Hu
Practical Attacks on Deep Neural Networks by Memory Trojaning. 1230-1243 - Kang Liu
Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors. 1244-1257 - Fuxun Yu
REIN the RobuTS: Robust DNN-Based Image Recognition in Autonomous Driving Systems. 1258-1271 - Jingwen Leng
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs". 1272
Volume 40, Number 7, July 2021
- Tinghuan Chen
Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building. 1273-1286 - Yangdi Lyu
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling. 1287-1300 - Rana Elnaggar
Security Against Data-Sniffing and Alteration Attacks in IJTAG. 1301-1314 - Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley
Detecting Failures and Attacks via Digital Sensors. 1315-1326 - Ning Lin
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks. 1327-1339 - Zhengguo Chen
CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile Memories. 1340-1353 - You Zhou
LiveSSD: A Low-Interference RAID Scheme for Hardware Virtualized SSDs. 1354-1366 - Chaoshu Yang
Making Frequent-Pattern Mining Scalable, Efficient, and Compact on Nonvolatile Memories. 1367-1380 - Peng Chen
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip. 1381-1394 - Zhaoyan Shen
Leveraging the Interplay of RAID and SSD for Lifetime Optimization of Flash-Based SSD RAID. 1395-1408 - Xuanqi Chen
Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks. 1409-1422 - Farhana Sharmin Snigdha
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. 1423-1436 - Lingjie Li
Efficient and Accuracy-Ensured Waveform Compression for Transient Circuit Simulation. 1437-1449 - Breytner Fernández-Mesa
Synchronization of Continuous Time and Discrete Events Simulation in SystemC. 1450-1463 - Haoyu Yang
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning. 1464-1475 - Yiyang Jiang
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. 1476-1488 - Gang Chen, Xiaoyu Song, Guowu Yang
A Formal Proof of PG Recurrence Equations of Parallel Adders. 1489-1494 - Chao Wang
Tinker: A Middleware for Deploying Multiple NN-Based Applications on a Single Machine. 1495-1499
Volume 40, Number 8, August 2021
- Dilip Kumar Maity
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. 1500-1510 - Tuotian Liao
An LDE-Aware gm/ID-Based Hybrid Sizing Method for Analog Integrated Circuits. 1511-1524 - Paul P. Sotiriadis
RF Switched-Capacitor Power Amplifier Modeling. 1525-1530 - Michael Zuzak
Trace Logic Locking: Improving the Parametric Space of Logic Locking. 1531-1544 - Fateme S. Hosseini
A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM. 1545-1558 - Davide Pala
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems. 1559-1572 - Palash Das
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs. 1573-1585 - Peng Gu
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. 1586-1599 - Michael Canesche
TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs. 1600-1612 - Jinyu Wang
DUPRFloor: Dynamic Modeling and Floorplanning for Partially Reconfigurable FPGAs. 1613-1625 - Foisal Ahmed
Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling. 1626-1639 - Shiping Wen
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network. 1640-1647 - Yun Liang
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs. 1648-1661 - Yan Liao
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect. 1662-1671 - Apostolos Stefanidis
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization. 1672-1686 - Tsung-Wei Huang
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. 1687-1700 - Huanhuan Ran, Shiping Wen
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification. 1701-1710 - Irith Pomeranz
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. 1711-1720 - Sachin Maheshwari
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. 1721-1725
Volume 40, Number 9, September 2021
- Abraham Peedikayil Kuruvila
Defending Hardware-Based Malware Detectors Against Adversarial Attacks. 1727-1739 - Nimisha Limaye
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking. 1740-1753 - Akhil Raj Baranwal
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems. 1754-1767 - Alberto Marchisio
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware. 1768-1781 - Yu Liang
iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices. 1782-1795 - Jiaqi Gu
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability. 1796-1809 - Lukas Burgholzer
Advanced Equivalence Checking for Quantum Circuits. 1810-1824 - Arighna Deb
Exploring the Potential Benefits of Alternative Quantum Computing Architectures. 1825-1835 - Jing Wang
Ant Colony Optimization-Based Thermal-Aware Adaptive Routing Mechanism for Optical NoCs. 1836-1849 - Minghua Shen
Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs. 1850-1863 - Weiyun Jiang
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. 1864-1873 - Shanlin Xiao
A Data-Driven Asynchronous Neural Network Accelerator. 1874-1886 - Alexander Jones
A Compact Gated-Synapse Model for Neuromorphic Circuits. 1887-1895 - Neng Zhang
Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model. 1896-1908 - Yi-Ting Lin, Iris Hui-Ru Jiang
Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials. 1909-1919 - Mengyun Liu, Fangming Ye, Xin Li, Krishnendu Chakrabarty
Board-Level Functional Fault Identification Using Streaming Data. 1920-1933 - Natsuki Urabe
Verifying Asymptotic Temporal Properties of Continuous-State Probabilistic Systems. 1934-1946 - Mohammadreza Asadikouhanjani
Enhancing the Utilization of Processing Elements in Spatial Deep Neural Network Accelerators. 1947-1951 - Tianming Ni
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC. 1952-1956
Volume 40, Number 10, October 2021
- Yuxiang Fu
Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs. 1957-1970 - Joshua Potter
Dynamic Radial Placement and Routing in Paper Microfluidics. 1971-1984 - Haocheng Ma
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive. 1985-1994 - Haocheng Li
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. 1995-2008 - Behnaz Ranjbar
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform. 2009-2023 - Runyu Zhang
Bridging Mismatched Granularity Between Embedded File Systems and Flash Memory. 2024-2035 - Levent Aksoy
Realization of Logic Functions Using Switching Lattices Under a Delay Constraint. 2036-2048 - Jilan Lin
Rescuing RRAM-Based Computing From Static and Dynamic Faults. 2049-2062 - Zhanwei Zhong
Enhancing the Reliability of MEDA Biochips Using IJTAG and Wear Leveling. 2063-2076 - Kang Liu
Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks. 2077-2089 - Maedeh Hemmat
AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs. 2090-2103 - Brian Crites
Reducing Microfluidic Very Large-Scale Integration (mVLSI) Chip Area by Seam Carving. 2104-2116 - Lalit Mohan Dani
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures. 2117-2127 - Jianli Chen, Yao-Wen Chang, Yen-Yi Wu:
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. 2128-2141 - Daeyeal Lee
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. 2142-2155 - Yibo Wu
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. 2170-2183 - Dewmini Sudara Marakkalage
Three-Input Gates for Logic Synthesis. 2184-2188 - Irith Pomeranz
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults. 2189-2193 - Wei Jiang
Attack-Aware Detection and Defense to Resist Adversarial Examples. 2194-2198 - Aditya Narayan
PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs. 2156-2169
Volume 40, Number 11, November 2021
- Ersin Alaybeyoglu
Analog Building Blocks Optimization for Low-Pass Filter of IEEE 802.11n Wireless LAN: OTA and CCII. 2199-2210 - Xinqian Zhang
Efficient Federated Learning for Cloud-Based AIoT Applications. 2211-2223 - Wen Sheng Lim
iCheck: Progressive Checkpointing for Intermittent Systems. 2224-2236 - Han Xu
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing. 2237-2250 - Mingyang Kou
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. 2251-2264 - Joshua Mack
RANC: Reconfigurable Architecture for Neuromorphic Computing. 2265-2278 - Zhe Lin
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. 2279-2292 - Miguel de Prado
Automated Design Space Exploration for Optimized Deployment of DNN on Arm Cortex-A CPUs. 2293-2305 - Xiaochen Peng
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. 2306-2319 - Wai-Kong Lee
GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation. 2320-2330 - Wei Li
OpenMPL: An Open-Source Layout Decomposer. 2331-2344 - Tao-Chun Yu, Shao-Yun Fang
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition. 2345-2356 - Zhuowei Wang
Activity-Driven Task Allocation in Energy-Constrained Heterogeneous GPUs Systems. 2357-2371 - Sidhartha Sankar Rout
WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip. 2372-2385 - Supriyo Maji
A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems. 2386-2399 - T. Vayssade
Low-Cost EVM Measurement of ZigBee Transmitters From 1-bit Undersampled Acquisition. 2400-2410 - Raouf Senhadji-Navarro
Methodology for Distributed-ROM-Based Implementation of Finite State Machines. 2411-2415 - Sayandeep Sanyal
Recurrence in Dense-Time AMS Assertions. 2416-2420 - Hui Wu, Zhe Su
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools. 2421-2425 - Ibrahim M. Elfadel
On the Stability of Analog ReLU Networks. 2426-2430
Volume 40, Number 12, December 2021
- Tianyu Chen
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance. 2431-2444 - Akashdeep Saha
ORACALL: An Oracle-Based Attack on Cellular Automata Guided Logic Locking. 2445-2454 - Dharamjeet
Beyond Write-Reduction Consideration: A Wear-Leveling-Enabled B⁺-Tree Indexing Scheme Over an NVRAM-Based Architecture. 2455-2466 - Imran Fareed
Update Frequency-Directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads. 2467-2480 - Jing Huang
A DVFS-Weakly Dependent Energy-Efficient Scheduling Approach for Deadline-Constrained Parallel Applications on Heterogeneous Systems. 2481-2494 - Yanan Sun
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing. 2495-2507 - Kalindu Herath
Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs. 2508-2521 - Gaurav Rajavendra Reddy
On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement. 2522-2527 - Mohammad Javad Dousti
Therminator 2: A Fast Thermal Simulator for Portable Devices. 2528-2541 - Alex Vidal-Obiols
Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods. 2542-2555 - Hao-Yu Chi
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. 2556-2567
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-04 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: