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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27
Volume 27, Number 1, January 2008
- Enrico Macii:
Editorial. 1-2 - Andrew B. Kahng, Kambiz Samadi:
CMP Fill Synthesis: A Survey of Recent Studies. 3-19 - Josep Carmona
, Jordi Cortadella
Encoding Large Asynchronous Controllers With ILP Techniques. 20-33 - Vamsi Vankamamidi, Marco Ottavi
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. 34-44 - Shrirang K. Karandikar, Sachin S. Sapatnekar
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. 45-58 - Ting Mei, Jaijeet S. Roychowdhury:
A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions. 59-69 - Chris C. N. Chu, Yiu-Chung Wong:
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. 70-83 - Muhammet Mustafa Ozdal, Martin D. F. Wong
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. 84-95 - Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
System-Level Dynamic Thermal Management for High-Performance Microprocessors. 96-108 - Shankar Mahadevan, Federico Angiolini, Jens Sparsø
A Reactive and Cycle-True IP Emulator for MPSoC Exploration. 109-122 - Daniel Arumí
Experimental Characterization of CMOS Interconnect Open Defects. 123-136 - Irith Pomeranz, Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. 137-146 - Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. 147-159 - Jaskirat Singh, Sachin S. Sapatnekar
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. 160-173 - Saibal Mukhopadhyay, Hamid Mahmoodi
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. 174-183 - Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis. 184-188 - Sushanta K. Mandal
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. 188-192 - Irith Pomeranz, Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. 193-197 - Weixin Wu, Michael S. Hsiao:
Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. 197-201
Volume 27, Number 2, February 2008
- Javid Jaffari, Mohab Anis:
Variability-Aware Bulk-MOS Device Design. 205-216 - R. Mahesh, A. Prasad Vinod
A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. 217-229 - Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
Defocus-Aware Leakage Estimation and Control. 230-240 - Ja Chun Ku, Yehea I. Ismail:
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. 241-248 - Ning Dong, Jaijeet S. Roychowdhury:
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations. 249-264 - Alexander Heldring, Juan Manuel Rius
Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction. 265-271 - Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David T. Blaauw:
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. 272-285 - Tung-Chieh Chen, Yao-Wen Chang
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. 286-294 - Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. 295-308 - Shantanu Dutt, Vinay Verma, Vishal Suthar:
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. 309-326 - Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 327-338 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. 339-351 - Zhanglei Wang, Krishnendu Chakrabarty
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns. 352-365 - Himanshu Jain, Daniel Kroening
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. 366-379 - Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. 380-393 - Hiren D. Patel, Sandeep K. Shukla
On Cosimulating Multiple Abstraction-Level System-Level Models. 394-398 - Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. 398-403 - Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa:
Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking. 403-407
Volume 27, Number 3, March 2008
- Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh:
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. 409-422 - Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. 423-435 - Dmitri Maslov
Quantum Circuit Simplification and Level Compaction. 436-444 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. 445-455 - Kin Cheong Sou
A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction. 456-469 - Ngai Wong:
Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations. 470-480 - Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw:
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. 481-494 - Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips:
Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation. 495-507 - Peter Hallschmid, Resve A. Saleh:
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. 508-515 - Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long:
Optimizing Thermal Sensor Allocation for Microprocessors. 516-527 - Kubilay Atasu
CHIPS: Custom Hardware Instruction Processor Synthesis. 528-541 - Hristo Nikolov, Todor P. Stefanov
Systematic and Automated Multiprocessor System Design, Programming, and Implementation. 542-555 - Chandan Karfa
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. 556-569 - Paolo Bernardi
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. 570-574 - Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. 574-578 - Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim:
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm. 578-583 - Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults. 583-587
Volume 27, Number 4, April 2008
- David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
Statistical Timing Analysis: From Basic Principles to State of the Art. 589-607 - Patrick H. Madden, David Z. Pan:
Guest Editorial. 608-609 - Vishal Khandelwal, Ankur Srivastava
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. 610-620 - Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. 621-632 - Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
Fast Dummy-Fill Density Analysis With Coupling Constraints. 633-642 - Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. 643-653 - Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
Effective Wire Models for X-Architecture Placement. 654-658 - Cheoljoo Jeong, Steven M. Nowick:
Technology Mapping and Cell Merger for Asynchronous Threshold Networks. 659-672 - Seok-Won Seong, Prabhat Mishra
Bitmask-Based Code Compression for Embedded Systems. 673-685 - Ryan Fung, Vaughn Betz, William Chow:
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. 686-697 - Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. 698-711 - Ying Wei, Alex Doboli:
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. 712-725 - Zhen Cao, Tong Jing, Jinjun Xiong
Fashion: A Fast and Accurate Solution to Global Routing Problem. 726-737 - Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid. 738-751 - Dmitri Maslov
Quantum Circuit Placement. 752-763 - Neil Kettle, Andy King:
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs. 764-777
Volume 27, Number 5, May 2008
- Paolo Maffezzoni:
Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators. 781-790 - Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Chuanjin Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. 791-802 - Natasa Miskov-Zivanov, Diana Marculescu
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits. 803-816 - Shweta Srivastava, Jaijeet S. Roychowdhury:
Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations. 817-830 - Xin Li, Yaping Zhan, Lawrence T. Pileggi:
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. 831-843 - Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang
Full-Chip Routing Considering Double-Via Insertion. 844-857 - Song Chen
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. 858-871 - Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
Track Routing and Optimization for Yield. 872-882 - Bo Hu, Chuanjin Richard Shi:
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. 883-892 - Diana Marculescu
Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems. 893-905 - Claudio Pinello, Luca P. Carloni
Fault-Tolerant Distributed Deployment of Embedded Control Software. 906-919 - Erkan Acar, Sule Ozev:
Defect-Oriented Testing of RF Circuits. 920-931 - Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Improving the Resolution of Single-Delay-Fault Diagnosis. 932-945 - Irith Pomeranz, Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. 946-957 - Jeong-Ho Han, In-Cheol Park
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. 958-962 - Xiaojun Ma, Fabrizio Lombardi:
Synthesis of Tile Sets for DNA Self-Assembly. 963-967 - Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta:
Accelerating Assertion Coverage With Adaptive Testbenches. 967-972 - Soheil Samii, Mikko Selkälä, Erik Larsson
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. 973-977 - Gülin Tulunay, Sina Balkir:
A Synthesis Tool for CMOS RF Low-Noise Amplifiers. 977-982
Volume 27, Number 6, June 2008
- Chong-Fatt Law, Bah-Hwee Gwee
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis. 985-998 - Dong Xiang, Yang Zhao, Krishnendu Chakrabarty
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. 999-1012 - Levent Aksoy
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. 1013-1026 - Javid Jaffari, Mohab Anis:
Statistical Thermal Profile Considering Process Variations: Analysis and Applications. 1027-1040 - Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. 1041-1054 - Zhe-Wei Jiang, Yao-Wen Chang
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing. 1055-1065 - Jarrod A. Roy, Igor L. Markov:
High-Performance Routing at the Nanometer Scale. 1066-1077 - Pramod Chandraiah, Rainer Dömer:
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding. 1078-1090 - Tarvo Raudvere, Ingo Sander
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. 1091-1103 - Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li:
Diagnosis of Multiple Scan Chain Timing Faults. 1104-1116 - S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness. 1117-1127 - Afshin Abdollahi, Massoud Pedram:
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions. 1128-1137 - Görschwin Fey
Automatic Fault Localization for Property Checking. 1138-1149 - Brajesh Kumar Kaushik
Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects. 1150-1154 - Sanghyun Park, Aviral Shrivastava
Register File Power Reduction Using Bypass Sensitive Compiler. 1155-1159 - Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting. 1159-1164
Volume 27, Number 7, July 2008
- Vijay Victor D'Silva, Daniel Kroening
A Survey of Automated Techniques for Formal Software Verification. 1165-1178 - Rafael Castro-López
An Integrated Layout-Synthesis Approach for Analog ICs. 1179-1189 - Anna Bernasconi
Logic Minimization and Testability of 2-SPP Networks. 1190-1202 - Lei Cheng, Deming Chen, Martin D. F. Wong
DDBDD: Delay-Driven BDD Synthesis for FPGAs. 1203-1213 - Taehoon Kim, Yungseon Eo:
Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines. 1214-1227 - Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. 1228-1240 - Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. 1241-1252 - Yiyu Shi, Jinjun Xiong
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. 1253-1263 - Soner Yaldiz, Alper Demir
Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. 1264-1277 - Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. 1278-1290 - Sari Onaissi, Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. 1291-1304 - Daniel Große
Analyzing Functional Coverage in Bounded Model Checking. 1305-1314 - Xiaoxi Xu, Cheng-Chew Lim
Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip. 1315-1328 - Rolf Drechsler
On Acceleration of SAT-Based ATPG for Industrial Designs. 1329-1333 - Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. 1333-1338 - Jing-Ling Yang, Qiang Xu
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction. 1338-1343 - Hao Zheng, Jared Ahrens, Tian Xia:
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification. 1343-1347
Volume 27, Number 8, August 2008
- Jason Cong, Min Xie:
A Robust Mixed-Size Legalization and Detailed Placement Algorithm. 1349-1362 - Chih-Hung Liu
An Efficient Graph-Based Algorithm for ESD Current Path Analysis. 1363-1375 - Maharaj Mukherjee, Kanad Chakraborty:
A Randomized Greedy Method for Rectangular-Pattern Fill Problems. 1376-1384 - Uday Padmanabhan, Janet Meiling Wang, Jiang Hu:
Robust Clock Tree Routing in the Presence of Process Variations. 1385-1397 - Peter Spindler, Ulf Schlichtmann
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. 1398-1411 - Giovanni Agosta
Static Analysis of Transaction-Level Communication Models. 1412-1424 - Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. 1425-1438 - Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. 1439-1452 - Ozgur Sinanoglu
Isolation Techniques for Soft Cores. 1453-1466 - Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li:
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time. 1467-1478 - Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph:
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. 1479-1492 - Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra:
A Fast Exploration Procedure for Analog High-Level Specification Translation. 1493-1497 - King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction. 1498-1502 - Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Self-Adaptive Data Caches for Soft-Error Reliability. 1503-1507 - Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang:
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method. 1508-1513 - Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. 1513-1517
Volume 27, Number 9, September 2008
- Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity Analysis for Oscillators. 1521-1534 - Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. 1535-1544 - Yao-Joe Joseph Yang, Chi-Wei Kuo:
Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique. 1545-1554 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
Input Vector Reordering for Leakage Power Reduction in FPGAs. 1555-1564 - Aijiao Cui, Chip-Hong Chang
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. 1565-1570 - Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng:
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. 1571-1582 - Hiran Tennakoon, Carl Sechen:
Nonconvex Gate Delay Modeling and Delay Optimization. 1583-1594 - Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. 1595-1606 - Ulrich Brenner, Markus Struzyna, Jens Vygen:
BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms. 1607-1620 - Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. 1621-1634 - Andrew B. Kahng, Chul-Hong Park, Xu Xu:
Fast Dual-Graph-Based Hotspot Filtering. 1635-1642 - Tsung-Hsien Lee, Ting-Chi Wang:
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing. 1643-1656 - Munkang Choi, Linda S. Milor
Diagnosis of Optical Lithography Faults With Product Test Sets. 1657-1669 - Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang:
Automatic Verification of External Interrupt Behaviors for Microprocessor Design. 1670-1683 - J.-C. Guo, Y.-M. Lin:
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs. 1684-1688 - Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan:
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. 1689-1692 - Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang:
Testing Transition Delay Faults in Modified Booth Multipliers. 1693-1697
Volume 27, Number 10, October 2008
- Wayne H. Wolf, Ahmed Amine Jerraya, Grant Martin:
Multiprocessor System-on-Chip (MPSoC) Technology. 1701-1713 - Minsik Cho, David Z. Pan:
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. 1714-1724 - Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. 1725-1736 - Alessandro Cimatti
Symbolic Compilation of PSL. 1737-1750 - Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. 1751-1760 - Ajay Kumar Verma, Philip Brisk
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. 1761-1774 - Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song:
Transforming Cyclic Circuits Into Acyclic Equivalents. 1775-1787 - Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh:
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. 1788-1797 - Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram:
Charge Recycling in Power-Gated CMOS Circuits. 1798-1811 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel:
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. 1812-1825 - Khaled R. Heloue, Farid N. Najm:
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models. 1826-1839 - Andrew Labun, Karan Jagjitkumar:
Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect. 1840-1851 - Jin Sun, Jun Li, Dongsheng Ma, Janet Meiling Wang:
Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty. 1852-1865 - Chen-Ling Chou, Ümit Y. Ogras
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels. 1866-1879 - Guo Yu, Wei Dong, Zhuo Feng, Peng Li:
Statistical Static Timing Analysis Considering Process Variation Model Uncertainty. 1880-1890 - Kian Haghdad, Mohab Anis:
Design-Specific Optimization Considering Supply and Threshold Voltage Variations. 1891-1901
Volume 27, Number 11, November 2008
- Tao Xu, Krishnendu Chakrabarty
A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips. 1905-1917 - Yang Yi, Peng Li, Vivek Sarin, Weiping Shi:
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics. 1918-1927 - Ping-Hung Yuh, Chia-Lin Yang
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. 1928-1941 - Yung-Chih Chen, Chun-Yao Wang:
An Implicit Approach to Minimizing Range-Equivalent Circuits. 1942-1955 - Jun Seomun, Jae-Hyun Kim, Youngsoo Shin:
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. 1956-1968 - Yongsoo Joo
Energy and Performance Optimization of Demand Paging With OneNAND Flash. 1969-1982 - Mohamed H. Abu-Rahma, Mohab Anis:
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations. 1983-1995 - Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. 1996-2006 - Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. 2007-2016 - Michael D. Moffitt:
MaizeRouter: Engineering an Effective Global Router. 2017-2026 - Seda Ogrenci Memik, Nikolaos Bellas
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. 2027-2038 - Seongmoon Wang, Wenlong Wei:
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability. 2039-2052 - M. Haykel Ben Jamaa, Kirsten E. Moselund
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. 2053-2067 - Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz:
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants. 2068-2082 - Sertac Cinel, Cüneyt F. Bazlamaçci
A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem. 2083-2087 - Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang:
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric. 2088-2092 - Ho Fai Ko, Nicola Nicolici:
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. 2092-2097 - Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. 2097-2101
Volume 27, Number 12, December 2008
- David Z. Pan, Gi-Joon Nam:
Guest Editorial. 2105-2106 - Stephen Plaza, Igor L. Markov, Valeria Bertacco:
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. 2107-2119 - Hosung Kim, John Lillis:
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs. 2120-2132 - Jason Cong, Guojie Luo, Eric Radke:
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. 2133-2144 - Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
Metal-Density-Driven Placement for CMP Variation and Routability. 2145-2155 - David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. 2156-2168 - Jieyi Long, Hai Zhou, Seda Ogrenci Memik:
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. 2169-2182 - Yifang Liu, Jiang Hu, Weiping Shi:
Buffering Interconnect for Multicore Processor Designs. 2183-2196 - Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion. 2197-2208 - Tobias Massier
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. 2209-2222 - David Walter
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. 2223-2235 - Tomasz S. Czajkowski, Stephen Dean Brown:
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. 2236-2249 - Roxana Ionutiu, Joost Rommes, Athanasios C. Antoulas:
Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation. 2250-2263 - Lin Xie, Azadeh Davoodi:
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. 2264-2276 - Rebecca L. Collins, Luca P. Carloni
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems. 2277-2290 - Chunrong Song, Spyros Tragoudas:
Identification of Critical Executable Paths at the Architectural Level. 2291-2302 - Ozgur Sinanoglu
Scan Architecture With Align-Encode. 2303-2316 - Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. 2317-2330
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