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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 39
Volume 39, Number 1, January 2020
- António Canelas
, Ricardo Póvoa
FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. 1-13 - Xiaoxue Sun
A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design. 14-24 - Ahmad Shabani
PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability. 25-33 - Zhipeng Guo
Table Recomputation-Based Higher-Order Masking Against Horizontal Attacks. 34-44 - Dmitry Utyamishev
Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip. 45-55 - Bohun Seo
Freezing: Eliminating Unnecessary Drawing Computation for Low Power. 56-61 - Yuncheng Guo, Yu Hua
A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory. 62-74 - Chen Li
A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing. 75-87 - Yue Ma
Online Resource Management for Improving Reliability of Real-Time Systems on "Big-Little" Type MPSoCs. 88-100 - Santiago Pagani
Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey. 101-116 - Lei Deng
SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars. 117-130 - Duo Liu
Downsizing Without Downgrading: Approximated Dynamic Time Warping on Nonvolatile Memories. 131-144 - Giuseppe Tagliavini
FlexFloat: A Software Library for Transprecision Computing. 145-156 - Jiayi Weng
URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips. 157-170 - Jack Tang
Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips. 171-184 - Zonghui Li
Time-Triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches. 185-198 - Song Chen
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. 199-212 - Lucas Machado
Support-Reducing Decomposition for FPGA Mapping. 213-224 - Alessandro Zanco
Enforcing Passivity of Parameterized LTI Macromodels via Hamiltonian-Driven Multivariate Adaptive Sampling. 225-238 - Liyang Lai
GPGPU-Based ATPG System: Myth or Reality? 239-247 - Binod Kumar
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. 248-261 - Irith Pomeranz
Multicycle Broadside and Skewed-Load Tests for Test Compaction. 262-266 - Junyan Qian
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays. 267-271 - Siamack BeigMohammadi
Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug. 272-276 - Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo
Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability". 277
Volume 39, Number 2, February 2020
- Umamaheswara Rao Tida, Cheng Zhuo
Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking. 281-293 - Ibtissem Seghaier
Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation. 294-307 - Jae-Won Jang
Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering. 308-320 - Li-Pin Chang
Current-Aware Flash Scheduling for Current Capping in Solid State Disks. 321-334 - Mingze Gao
Estimate and Recompute: A Novel Paradigm for Approximate Computing on Data Flow Graphs. 335-345 - Daniel Peroni
Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier. 346-358 - Yasamin Moradi
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis. 359-372 - Shuo-Han Chen
A Partial Page Cache Strategy for NVRAM-Based Storage Devices. 373-386 - Andreas Grimmer
Automatic Droplet Sequence Generation for Microfluidic Networks With Passive Droplet Routing. 387-396 - Valerio Tenace
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies. 397-410 - Minghua Shen
Serial-Equivalent Static and Dynamic Parallel Routing for FPGAs. 411-423 - Yufei Ma
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. 424-437 - Tao Luo
An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM. 438-450 - Shigetaka Kumashiro
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. 451-463 - Panagiota Papavramidou, Michael Nicolaidis
Iterative Diagnosis Approach for ECC-Based Memory Repair. 464-477 - Kwangsoo Han
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. 478-491 - Mehran Goli
Automated Nonintrusive Analysis of Electronic System Level Designs. 492-505 - Yang Yu
A Post-Bond TSV Test Method Based on RGC Parameters Measurement. 506-519 - Mayler G. A. Martins
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. 520-532 - Debjit Pal
Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. 533-546 - Jiali Luan, Zheng Zhang
Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion. 547-551
Volume 39, Number 3, March 2020
- Mohammad Abdul Alim
Temperature Dependence of the Taylor Series Coefficients and Intermodulation Distortion Characteristics of GaN HEMT. 552-559 - Fábio Passos
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. 560-571 - Farzad Samie
Fast Operation Mode Selection for Highly Efficient IoT Edge Devices. 572-584 - Po-Hao Huang, Ya-Shu Chen
QT-Adaptation Engine: Adaptive QoS-Aware Scheduling and Governing in Thermally Constrained Mobile Devices. 585-598 - Yazhi Feng
Multiple Subpage Writing FTL in MLC by Exploiting Dual Mode Operations. 599-612 - Qin Wang
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. 613-625 - Peng Yang
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems. 626-639 - Zhifei Wang
A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers. 640-653 - Sanbao Su, Chen Zou, Weijiang Kong
A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis. 654-669 - Sedigheh Kouhpayeh-Zadeh-Esfahani
Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Transmission Line Excited by an Arbitrary Modulated Signal. 670-674 - Yen-Yu Su, Shuo-Hui Wang, Wei-Liang Wu, Mark Po-Hung Lin
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction. 675-685 - Zuomin Zhu
Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model. 686-699 - Shi Jin
Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System. 700-713 - Ying Zhang
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. 714-727 - Gabriel A. G. Andrade
Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification. 728-741 - Irith Pomeranz
Reverse Low-Power Broadside Tests. 742-746 - Augusto Neutzling
maj-n Logic Synthesis for Emerging Technology. 747-751
Volume 39, Number 4, April 2020
- Indrani Roy
SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations. 752-765 - Abhrajit Sengupta
Logic Locking With Provable Security Against Power Analysis Attacks. 766-778 - Mohsen Ansari
Peak-Power-Aware Energy Management for Periodic Real-Time Applications. 779-788 - Xiaotao Jia, Jianlei Yang
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. 789-802 - Bi Wu
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. 803-815 - Sukanta Bhattacharjee
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip. 816-829 - Dekui Wang
ParRA: A Shared Memory Parallel FPGA Router Using Hybrid Partitioning Approach. 830-842 - Yufei Ma
Performance Modeling for CNN Inference Accelerators on FPGA. 843-856 - Yun Liang
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs. 857-870 - Winston Haaswijk
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. 871-884 - Sheriff Sadiqbatcha
Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs. 885-894 - Fulya Kaplan
LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency. 895-908 - Fei Wu, Meng Zhang
Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash. 909-921 - Neetu Jindal
Enhancing Network-on-Chip Performance by Reusing Trace Buffers. 922-935 - Irith Pomeranz
Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults. 936-945 - Ming Yang
Reliable Macromodel Generation for the Capacitance Extraction Based on Macromodel-Aware Random Walk Algorithm. 946-951
Volume 39, Number 5, May 2020
- Danil Sokolov
Automating the Design of Asynchronous Logic Control for AMS Electronics. 952-965 - Ahcène Bounceur
Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model. 966-976 - Xuanqi Chen
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect. 977-990 - Qian Zhang
ApproxIt: A Quality Management Framework of Approximate Computing for Iterative Methods. 991-1002 - Jack Tang
Analysis and Design of Tamper-Mitigating Microfluidic Routing Fabrics. 1003-1016 - Othon Tomoutzoglou
Efficient Job Offloading in Heterogeneous Systems Through Hardware-Assisted Packet-Based Dispatching and User-Level Runtime Infrastructure. 1017-1030 - Dalin Li
An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs. 1031-1044 - Jingwen Ding
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits. 1045-1058 - Mohammad Reza Rohanipoor
Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach. 1059-1072 - Sitansusekhar Roymohapatra
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. 1073-1083 - Chris Yakopcic
Memristor Model Optimization Based on Parameter Extraction From Device Characterization Data. 1084-1095 - Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang
Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation. 1096-1108 - Prachi Joshi
Approaches for Assigning Offsets to Signals for Improving Frame Packing in CAN-FD. 1109-1122 - Shaahin Angizi
MRIMA: An MRAM-Based In-Memory Accelerator. 1123-1136 - Sameh El-Ashry
On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment. 1137-1150
Volume 39, Number 6, June 2020
- Bon Woong Ku
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs. 1151-1164 - Sheng-En David Lin, Dae Hyun Kim
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design. 1165-1176 - Aysa Fakheri Tabrizi
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist. 1177-1190 - Song Chen
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips. 1191-1204 - Daifeng Guo
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography. 1205-1216 - Gengjie Chen
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. 1217-1230 - Raphael Andreoni Camponogara Viera
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection. 1231-1244 - Peishan Tu
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. 1245-1257 - Brent J. Maundy
Automatic Generation of Differential-Input Differential-Output Second-Order Filters Based on a Differential Pair. 1258-1271 - Mohammad Hosseinabady
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis. 1272-1285 - Shuo-Han Chen
Beyond Address Mapping: A User-Oriented Multiregional Space Management Design for 3-D NAND Flash Memory. 1286-1299 - Nirmal Prajapati
Optimization Approach to Accelerator Codesign. 1300-1313 - Xing Huang
Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips. 1314-1327 - Kyle Kuan
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. 1328-1339 - Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. 1340-1345 - Maciej J. Ciesielski
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. 1346-1357
Volume 39, Number 7, July 2020
- Ebadollah Taheri
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips. 1358-1371 - Ye X. Ding, Florin Burcea
PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs. 1372-1385 - Zonghui Li
Model-Based Adaptation of Mixed-Criticality Multiservice Systems for Extreme Physical Environments. 1386-1399 - Hai Wang
Leakage-Aware Predictive Thermal Management for Multicore Systems Using Echo State Network. 1400-1413 - Yi Cai
Low Bit-Width Convolutional Neural Network on RRAM. 1414-1427 - Jieru Zhao
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. 1428-1441 - Junzhong Shen
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. 1442-1455 - Ankur Sharma
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. 1456-1469 - Yi Wu
ALFANS: Multilevel Approximate Logic Synthesis Framework by Approximate Node Simplification. 1470-1483 - Mohammad Saber Golanbari
Selective Flip-Flop Optimization for Reliable Digital Circuit Design. 1484-1497 - Cheng Zhuo
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. 1498-1510 - Ying Chen
Semisupervised Hotspot Detection With Self-Paced Multitask Learning. 1511-1523 - Gianpiero Cabodi
Reducing Interpolant Circuit Size Through SAT-Based Weakening. 1524-1531 - Rongyang Liu, José G. Delgado-Frias
Online Firmware Functional Validation Scheme Using Colored Petri Net Model. 1532-1545 - Atef Ibrahim
Unified and Scalable Digit-Serial Systolic Array for Multiplication and Division Over GF (2m). 1546-1549
Volume 39, Number 8, August 2020
- Giovanni Agosta, Alessandro Barenghi
Compiler-Based Techniques to Secure Cryptographic Embedded Software Against Side-Channel Attacks. 1550-1554 - Onur Mutlu
RowHammer: A Retrospective. 1555-1571 - Emil Stefanov, Marten van Dijk
A Retrospective on Path ORAM. 1572-1576 - Mohamed El Massad
The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures. 1577-1590 - Satwik Patnaik
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. 1591-1606 - Kyle Juretus
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack. 1607-1620 - Zhufei Chu
Advanced Functional Decomposition Using Majority and Its Applications. 1621-1634 - Andreas Voigt
Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems. 1635-1648 - Chunfeng Cui
High-Dimensional Uncertainty Quantification of Electronic and Photonic IC With Non-Gaussian Correlated Process Variations. 1649-1661 - Wei-Chun Chang, Iris Hui-Ru Jiang
iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation. 1662-1673 - Myoungsoo Jung
Design of a Host Interface Logic for GC-Free SSDs. 1674-1687 - Gian Mayuga
Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC. 1688-1698 - Yingdi Liu
Deterministic Stellar BIST for Automotive ICs. 1699-1710 - Debjit Pal
Assertion Ranking Using RTL Source Code Analysis. 1711-1724 - Syed Ali Asadullah Bukhari
Toward Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques Under Multithreaded Workloads. 1725-1738 - Irith Pomeranz
Broadside Tests for Transition and Stuck-At Faults. 1739-1743 - Daeyeon Kim
Compact Topology-Aware Bus Routing for Design Regularity. 1744-1749
Volume 39, Number 9, September 2020
- Ing-Chao Lin
Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture. 1750-1763 - Shengyuan Zhou
ParaML: A Polyvalent Multicore Accelerator for Machine Learning. 1764-1777 - Alessandro Barenghi
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks. 1778-1791 - Zhiyong Zhang
UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache. 1792-1805 - Bing Wu
A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches. 1806-1819 - Zhehui Wang
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors. 1820-1833 - Suresh Durai
Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase-Change Memory Device. 1834-1840 - Weidong Cao
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion. 1841-1854 - Taehyun Kwon
Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement. 1855-1865 - Zoha Pajouhi
Ultralow Power Nonvolatile Logic Based on Spin-Orbit and Exchange Coupled Nanowires. 1866-1874 - Qi Nie
MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications. 1875-1888 - Junki Park
Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators. 1889-1901 - Gengjie Chen
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. 1902-1915 - Rassul Bairamkulov
Power Delivery Exploration Methodology Based on Constrained Optimization. 1916-1924 - Minho Cheong
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults. 1925-1934 - Shi Jin
Self-Learning and Efficient Health-Status Analysis for a Core Router System. 1935-1948
Volume 39, Number 10, October 2020
- Abhishek Chakraborty
Keynote: A Disquisition on Logic Locking. 1952-1972 - Minxuan Zhou, Andreas Prodromou, Rui Wang
Temperature-Aware DRAM Cache Management - Relaxing Thermal Constraints in 3-D Systems. 1973-1986 - Yangguang Cui, Kun Cao
Augmented Cross-Entropy-Based Joint Temperature Optimization of Real-Time 3-D MPSoC Systems. 1987-1999 - Hossein Eslahi
An Analytical Model for Hot Carrier Induced Long-Term Degradation in Power Amplifiers. 2000-2005 - Sabyasachi Deyati
Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware. 2006-2019 - John Vista
High Frequency Meminductor Emulator Employing VDTA and its Application. 2020-2028 - Zhengqi Gao
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. 2029-2041 - Federico Pittino
Robust Identification of Thermal Models for In-Production High-Performance-Computing Clusters With Machine Learning-Based Data Selection. 2042-2054 - Xin Zheng
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System. 2055-2066 - Yu Liu, Chao Peng
Schedulability Analysis of Engine Control Systems With Dynamic Switching Speeds. 2067-2080 - Lei Bu
Scenario-Based Online Reachability Validation for CPS Fault Prediction. 2081-2094 - Kun Cao
Exploring Renewable-Adaptive Computation Offloading for Hierarchical QoS Optimization in Fog Computing. 2095-2108 - Pierluigi Nuzzo
Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures. 2109-2123 - Lu Zhang
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel. 2124-2137 - Junye Shi, Yang Lu
Approximation Attacks on Strong PUFs. 2138-2151 - Huanyu Wang
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding. 2152-2165 - Changhai Ou
A First Study of Compressive Sensing for Side-Channel Leakage Sampling. 2166-2177 - Hsiao-Yu Chiang
LOOPLock: Logic Optimization-Based Cyclic Logic Locking. 2178-2191 - Chaofei Yang
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. 2192-2205 - Basireddy Karunakar Reddy
AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores. 2206-2217 - Yue Ma
Improving Reliability of Soft Real-Time Embedded Systems on Integrated CPU and GPU Platforms. 2218-2229 - Congming Gao
Aging Capacitor Supported Cache Management Scheme for Solid-State Drives. 2230-2239 - Won-Kyung Kang
$Q$ -Value Prediction for Reinforcement Learning Assisted Garbage Collection to Reduce Long Tail Latency in SSD. 2240-2253 - Siqi Wang
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors. 2254-2267 - Mohsen Imani
QuantHD: A Quantization Framework for Hyperdimensional Computing. 2268-2278 - Jingchen Zhu
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. 2279-2292 - Zimeng Zhou
Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems. 2293-2306 - Shibarchi Majumder
Ærø: A Platform Architecture for Mixed-Criticality Airborne Systems. 2307-2318 - Xu Jiang
Decomposition-Based Real-Time Scheduling of Parallel Tasks on Multicores Platforms. 2319-2332 - Wei Zhang
Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches. 2333-2346 - Wen Wen
Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory. 2347-2360 - Aayush Ankit
TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks. 2361-2374 - Abhoy Kole
Improved Mapping of Quantum Circuits to IBM QX Architectures. 2375-2383 - Yaoyao Ye
Thermal-Aware Design and Simulation Approach for Optical NoCs. 2384-2395 - Quan Deng
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. 2396-2409 - Jiaqing Jiang
Structured Decomposition for Reversible Boolean Functions. 2410-2421 - Mohsen Imani
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training. 2422-2433 - Rotem Ben Hur
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. 2434-2447 - Baogang Zhang
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs. 2448-2460 - Qi Yu
HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs. 2461-2474 - Tung-Liang Lin
A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees. 2475-2488 - Ying Zhu, Xing Huang
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. 2489-2502 - Swagath Venkataramani
Logic Synthesis of Approximate Circuits. 2503-2515 - Dan Feng, Jie Xu
A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories. 2516-2529 - Chunfeng Liu, Bing Li
Test Generation for Flow-Based Microfluidic Biochips With General Architectures. 2530-2543 - Weiqing Ji, Tsung-Yi Ho
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network. 2544-2557 - Omid Akbari
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture. 2558-2571 - Ryutaro Doi
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. 2572-2587 - Minghua Shen
Entropy-Directed Scheduling for FPGA High-Level Synthesis. 2588-2601 - Shathanaa Rajmohan
Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities. 2602-2614 - Shuangnan Liu
Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows. 2615-2627 - Benjamin Carrión Schäfer
High-Level Synthesis Design Space Exploration: Past, Present, and Future. 2628-2639 - Yaping Li
An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration. 2640-2653 - Hang Lu
Architecting Effectual Computation for Machine Learning Accelerators. 2654-2667 - Yu Xing
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators. 2668-2681 - Tung-Che Liang
Multitarget Sample Preparation Using MEDA Biochips. 2682-2695 - Gerold Fink
Robustness Analysis for Droplet-Based Microfluidic Networks. 2696-2707 - Lingxuan Shao
Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips. 2708-2721 - Mohammed Al-daloo
Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements. 2722-2734 - Xinyuan Wang
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation. 2735-2748 - Yuri Ardesi
SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing. 2749-2760 - Min Su Kim, Yong Wook Kim, Tae Hee Han
System-Level Signal Analysis Methodology for Optical Network-on-Chip Using Linear Model-Based Characterization. 2761-2771 - Dennis D. Weller
Bayesian Optimized Mixture Importance Sampling for High-Sigma Failure Rate Estimation. 2772-2783 - Matthias Függer
A Faithful Binary Circuit Model. 2784-2797 - Changqing Xu
SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch-Router Architecture. 2798-2811 - Geoffrey J. Coram
Flicker Noise Formulations in Compact Models. 2812-2821 - Haoyu Yang
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. 2822-2834 - Dimitrios Mangiras
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering. 2835-2848 - Hao Geng
SRAF Insertion via Supervised Dictionary Learning. 2849-2859 - Hamed Fatemi, Andrew B. Kahng, Hyein Lee
Heuristic Methods for Fine-Grain Exploitation of FDSOI. 2860-2871 - Pascal Van Cleeff
BonnCell: Automatic Cell Layout in the 7-nm Era. 2872-2885 - Or Maltabashi
Physically Aware Affinity-Driven Multiplier Implementation. 2886-2897 - Tae-Hee You
Multitoken-Based Power Management for NAND Flash Storage Devices. 2898-2910 - Chengjin Tian, Yongkun Li
Popularity-Based Online Scaling for RAID Systems Under General Settings. 2911-2924 - Mingxi Cheng
H₂O-Cloud: A Resource and Quality of Service-Aware Task Scheduling Framework for Warehouse-Scale Data Centers. 2925-2937 - Tianming Ni
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults. 2938-2951 - Michele Portolan
Automated Testing Flow: The Present and the Future. 2952-2963 - Yu Huang
Low Cost Hypercompression of Test Data. 2964-2975 - Mohammad Ebrahimi
Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information. 2976-2989 - Peikun Wang
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns. 2990-2999 - Liting Yu
NBTI and HCI Aging Prediction and Reliability Screening During Production Test. 3000-3011 - Irith Pomeranz
Globally Functional Transparent-Scan Sequences. 3012-3022 - Young-Woo Lee
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks. 3023-3034 - Irith Pomeranz
New Targets for Diagnostic Test Generation. 3035-3043 - Mason Chern, Shih-Wei Lee, Shi-Yu Huang
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. 3044-3055 - Abhishek Koneru
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs. 3056-3066 - Benjamin Viale
Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part I. 3067-3080 - Vinicius N. Possani
Parallel Combinational Equivalence Checking. 3081-3092 - Tobias Ludwig
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows. 3093-3106 - Benjamin Viale
Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part II. 3107-3117 - Weiqiang Liu
High Performance Modular Multiplication for SIDH. 3118-3122 - Jianing Deng
Energy-Efficient Real-Time UAV Object Detection on Embedded Platforms. 3123-3127 - Wei-Che Wang
Reverse Engineering for 2.5-D Split Manufactured ICs. 3128-3133 - Rajit Manohar
Exact Timing Analysis for Asynchronous Circuits With Multiple Periods. 3134-3138 - Irith Pomeranz
Functional Broadside Tests Under Broadcast Scan. 3139-3143 - Zhengqi Gao
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. 3144-3148
Volume 39, Number 11, November 2020
- Mark Sagi
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. 3152-3164 - Jinfeng Li
ABCFI: Fast and Lightweight Fine-Grained Hardware-Assisted Control-Flow Integrity. 3165-3176 - Yibo Wu
Aggressive Fine-Grained Power Gating of NoC Buffers. 3177-3189 - Taha Belkhouja
Analyzing Deep Learning for Time-Series Data Through Adversarial Lens in Mobile and IoT Applications. 3190-3201 - M. Akif Özkan
AnyHLS: High-Level Synthesis With Partial Evaluation. 3202-3214 - Rupak Majumdar
Assume-Guarantee Distributed Synthesis. 3215-3226 - Marcus Pirron
Automated Controller and Sensor Configuration Synthesis Using Dimensional Analysis. 3227-3238 - Yongwoo Lee
AxFTL: Exploiting Error Tolerance for Extending Lifetime of NAND Flash Storage. 3239-3249 - Elbruz Ozen
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection. 3250-3262 - Chao Wu
Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices. 3263-3275 - Jiachen Wang
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming. 3276-3287 - Ivan Ruchkin
Compositional Probabilistic Analysis of Temporal Properties Over Stochastic Detectors. 3288-3299 - Mahesh Balasubramanian
CRIMSON: Compute-Intensive Loop Acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs. 3300-3310 - Gaddisa Olani Ganfure
DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices. 3311-3322 - Chao Huang
Divide and Slide: Layer-Wise Refinement for Output Range Analysis of Deep Neural Networks. 3323-3335 - Jing Huang
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan. 3336-3347 - Homa Aghilinasab
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms. 3348-3360 - Sami Salamin
Dynamic Power and Energy Management for NCFET-Based Processors. 3361-3372 - Renato Cordeiro, Dhruv Gajaria
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. 3373-3384 - Jinghao Sun, Rongxiao Shi, Kexuan Wang, Nan Guan
Efficient Feasibility Analysis for Graph-Based Real-Time Task Systems. 3385-3397 - Jinfeng Li
Efficient Return Address Verification Based on Dislocated Stack. 3398-3407 - Shixuan Zheng
Efficient Scheduling of Irregular Network Structures on CNN Accelerators. 3408-3419 - Jian Gao
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking. 3420-3432 - Zhendong Wang
Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. 3433-3444 - Yawen Wu
Enabling On-Device CNN Training by Self-Supervised Instance Filtering and Error Map Pruning. 3445-3457 - H. Seckin Demir
Energy-Efficient Image Recognition System for Marine Life. 3458-3466 - Kong-Kiat Yong
Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs. 3467-3478 - Chih-Kai Kang
Everything Leaves Footprints: Hardware Accelerated Intermittent Deep Inference. 3479-3491 - Gregor Peach, Runyu Pan, Zhuoyi Wu
eWASM: Practical Software Fault Isolation for Reliable Embedded Devices. 3492-3505 - Yehan Ma
Exploring Edge Computing for Multitier Industrial Control. 3506-3518 - Virinchi Roy Surabhi
Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging. 3519-3530 - Tung-Che Liang
Extending the Lifetime of MEDA Biochips by Selective Sensing on Microelectrodes. 3531-3543 - Martin Kristien
Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems. 3544-3554 - Feng Yu
Fast Attack-Resilient Distributed State Estimator for Cyber-Physical Systems. 3555-3565 - Jack Miskelly
Fast DRAM PUFs on Commodity Devices. 3566-3576 - Vikkitharan Gnanasambandapillai
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. 3577-3588 - Fanrong Li
FSA: A Fine-Grained Systolic Accelerator for Sparse CNNs. 3589-3600 - Rachmad Vidya Wicaksana Putra
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks. 3601-3613 - Guangli Li
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices. 3614-3626 - Fei Wen
Hardware Memory Management for Future Mobile Hybrid Memory Systems. 3627-3637 - Quintin Fettes
Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning. 3638-3649 - Yilian Ribot González
HopliteRT*: Real-Time NoC for FPGA. 3650-3661 - Sergi Vilardell
HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs. 3662-3673 - Zhenya Zhang
Hybrid System Falsification Under (In)equality Constraints via Search Space Transformation. 3674-3685 - Jiwon Kim
Hydrone: Reconfigurable Energy Storage for UAV Applications. 3686-3697 - Vipin Kumar Kukkala
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems. 3698-3710 - Songran Liu, Wei Zhang
LATICS: A Low-Overhead Adaptive Task-Based Intermittent Computing System. 3711-3723 - Yuechen Chen
Learning-Based Quality Management for Approximate Communication in Network-on-Chips. 3724-3735 - Lorenzo Ferretti
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. 3736-3747 - Faiq Khalid
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices. 3748-3761 - Gregory Stock, Juan A. Fraire
Managing Fleets of LEO Satellites: Nonlinear, Optimal, Efficient, Scalable, Usable, and Robust. 3762-3773 - Nicolas Belleville
Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation. 3774-3786 - Haitong Wang, Neil C. Audsley, Xiaobo Sharon Hu
Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures. 3787-3798 - Md Jubaer Hossain Pantho
MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC. 3799-3808 - Ezio Bartocci
Mining Shape Expressions From Positive Examples. 3809-3820 - Elisabetta De Giovanni
Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms. 3821-3832 - Amir Hosein Afandizadeh Zargari
NEWERTRACK: ML-Based Accurate Tracking of In-Mouth Nutrient Sensors Position Using Spectrum-Wide Information. 3833-3841 - Hussam Amrouch
NPU Thermal Management. 3842-3855 - Yao-Wen Kang, Chun-Feng Wu
On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators. 3856-3867 - Konstantinos Mamouras
Online Signal Monitoring With Bounded Lag. 3868-3880 - S. R. Swamy Saranam Chongala
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities. 3881-3892 - Seunghyeok Jeon
Optimizing Discharge Efficiency of Reconfigurable Battery With Deep Reinforcement Learning. 3893-3905 - Ashikahmed Bhuiyan
Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information. 3906-3917 - Xiaofan Yu
Optimizing Sensor Deployment and Maintenance Costs for Large-Scale Environmental Monitoring. 3918-3930 - Jiwon Kim
Optrone: Maximizing Performance and Energy Resources of Drone Batteries. 3931-3943 - Bai Xue
PAC Model Checking of Black-Box Continuous-Time Dynamical Systems. 3944-3955 - Jun Li
Patch-Based Data Management for Dual-Copy Buffers in RAID-Enabled SSDs. 3956-3967 - Asif Ali Khan
Polyhedral Compilation for Racetrack Memories. 3968-3980 - Andreas Pavlogiannis
Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling. 3981-3992 - Chao Wu
Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices. 3993-4005 - Ming Hu
Quantitative Timing Analysis for Cyber-Physical Systems Using Uncertainty-Aware Scenario-Based Specifications. 4006-4017 - Sergiy Bogomolov
Reachability Analysis of Linear Hybrid Systems via Block Decomposition. 4018-4029 - Huize Li
ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory. 4030-4041 - Yachen Kong
Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions. 4042-4051 - Isaías B. Felzmann
Risk-5: Controlled Approximations for RISC-V. 4052-4063 - Anish Krishnakumar
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems. 4064-4077 - Orlando Arias, Dean Sullivan, Haoqi Shan, Yier Jin
SaeCAS: Secure Authenticated Execution Using CAM-Based Vector Storage. 4078-4089 - Bai Xue
Safety Verification for Random Ordinary Differential Equations. 4090-4101 - Changlong Li
SEAL: User Experience-Aware Two-Level Swap for Mobile Devices. 4102-4114 - Yun-Shan Hsieh, Po-Chun Huang
Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based Systems. 4115-4128 - Sarada Krithivasan
Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks. 4129-4141 - Nikhil Kumar Singh
Specification-Guided Automated Debugging of CPS Models. 4142-4153 - Weiwen Jiang
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start. 4154-4165 - Christoph W. Kessler
Static Scheduling of Moldable Streaming Tasks With Task Fusion for Parallel Systems With DVFS. 4166-4178 - Gang Chen
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network. 4179-4190 - Hazoor Ahmad
SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume. 4191-4204 - Mario Günzel
Suspension-Aware Earliest-Deadline-First Scheduling Analysis. 4205-4216 - Marco Siracusa
Tensor Optimization for High-Level Synthesis Design Flows. 4217-4228 - Steven Derrien, Thibaut Marty, Simon Rokicki
Toward Speculative Loop Pipelining for High-Level Synthesis. 4229-4239 - Paul Palomero Bernardo
UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting. 4240-4251 - Diksha Moolchandani
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors. 4252-4265 - Chun-Feng Wu
When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next? 4266-4277 - Gopinath Mahale
WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices. 4278-4289 - Xuan Wang
WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm. 4290-4302 - Raúl Camposano, Oliver Bringmann:
Wolfgang Rosenstiel. 4308
Volume 39, Number 12, December 2020
- Fikre Tsigabu Gebreyohannes
A gm/ID Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators. 4311-4324 - Zhenxin Zhao
An Automated Topology Synthesis Framework for Analog Integrated Circuits. 4325-4337 - Tom J. Smy
Integration of Traveling Wave Optical Device Models Into an MNA-Based Circuit Simulator. 4338-4350 - Ilho Myeong
A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models. 4351-4358 - Satyajit Mohapatra
Gradient Error Compensation in SC-MDACs. 4359-4374 - Fábio Passos
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications. 4375-4384 - Amir Mahdi Hosseini Monazzah
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation. 4385-4398 - Wei-Ming Chen
Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing. 4399-4412 - Guoqi Xie
Security-Aware Obfuscated Priority Assignment for CAN FD Messages in Real-Time Parallel Automotive Applications. 4413-4425 - Yunhao Xu, Yingjie Lao
Mathematical Modeling Analysis of Strong Physical Unclonable Functions. 4426-4438 - Abhrajit Sengupta
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective. 4439-4452 - Asmit De
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V. 4453-4465 - Satwik Patnaik
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. 4466-4481 - Grace Li Zhang
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. 4482-4495 - Ding Deng
Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure. 4496-4509 - Subodha Charles
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs. 4510-4523 - Aijiao Cui
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash. 4524-4536 - Jinghao Sun
Capacity Augmentation Function for Real-Time Parallel Tasks With Constrained Deadlines Under GEDF Scheduling. 4537-4548 - Yu-Pei Liang, Tseng-Yi Chen
B*-Sort: Enabling Write-Once Sorting for Nonvolatile Memory. 4549-4562 - Ruixiang Ma
BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction. 4563-4574 - Zhaoyan Shen
An Efficient Directory Entry Lookup Cache With Prefix-Awareness for Mobile Devices. 4575-4586 - Suzhen Wu, Weidong Zhu
GC-Steering: GC-Aware Request Steering and Parallel Reconstruction Optimizations for SSD-Based RAIDs. 4587-4600 - Sepideh Safari
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems. 4601-4610 - Yi Wang
Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory. 4611-4622 - Daniel Peroni
Data Reuse for Accelerated Approximate Warps. 4623-4634 - Saravanan Sethuraman
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. 4635-4644 - Govind Radhakrishnan
Monitoring Aging Defects in STT-MRAMs. 4645-4656 - Philipp Niemann
Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation. 4657-4668 - Hai Jin
Miss Penalty Aware Cache Replacement for Hybrid Memory Systems. 4669-4682 - Xiangzhen Zhou
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search. 4683-4694 - Renjie Yao
Toward a High-Performance and Low-Loss Clos-Benes-Based Optical Network-on-Chip Architecture. 4695-4706 - Yi Cai
Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems. 4707-4720 - Pengcheng Zhu
A Dynamic Look-Ahead Heuristic for the Qubit Mapping Problem of NISQ Computers. 4721-4735 - Ziru Li
RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation. 4736-4747 - Jinglan Liu
Binarizing Weights Wisely for Edge Intelligence: Guide for Partial Binarization of Deconvolution-Based Generators. 4748-4759 - Aseem Sayal
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs. 4760-4776 - Thibaut Marty
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection. 4777-4790 - Yazhu Lan
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks. 4791-4804 - Weiwen Jiang
Hardware/Software Co-Exploration of Neural Architectures. 4805-4815 - Xueyu Han, Jiajia Chen
A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture. 4816-4827 - Young-kyu Choi
FLASH: Fast, Parallel, and Accurate Simulator for HLS. 4828-4841 - Jochen Rust
A Hardware Generator for SORN Arithmetic. 4842-4853 - Vitaly G. Levashenko
Development of Programmable Logic Array for Multiple-Valued Logic Functions. 4854-4866 - Dong Wang
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs. 4867-4880 - Bosheng Liu
Swallow: A Versatile Accelerator for Sparse Neural Networks. 4881-4893 - Weihong Xu
Reconfigurable and Low-Complexity Accelerator for Convolutional and Generative Networks Over Finite Fields. 4894-4907 - Mohammed Shayan
Toward Secure Checkpointing for Micro-Electrode-Dot-Array Biochips. 4908-4920 - Zhanwei Zhong
IJTAG-Based Fault Recovery and Robust Microelectrode-Cell Design for MEDA Biochips. 4921-4934 - Ming Yang
Floating Random Walk Capacitance Solver Tackling Conformal Dielectric With On-the-Fly Sampling on Eight-Octant Transition Cubes. 4935-4943 - Zhuo Feng
GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis. 4944-4957 - Chunfeng Cui
Chance-Constrained and Yield-Aware Optimization of Photonic ICs With Non-Gaussian Correlated Process Variations. 4958-4970 - Fulin Peng, Handi Yu, Jun Tao
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. 4971-4984 - Hyun-jeong Kwon
Additive Statistical Leakage Analysis Using Exponential Mixture Model. 4985-4998 - Xiao Shi
An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis. 4999-5010 - Di Gao
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures. 5011-5024 - Nahid Mirzaie
A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits. 5025-5031 - Xun Jiao
LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units. 5032-5041 - Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. 5042-5055 - Abhishek Patyal
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. 5056-5068 - Yuzhe Ma
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization. 5069-5082 - Yibo Lin
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. 5083-5096 - Dongwon Park
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules. 5097-5110 - Monzurul Islam Dewan
NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization. 5111-5122 - Emilio Wuerges
3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing. 5123-5127 - Ziran Zhu
Mixed-Cell-Height Legalization Considering Technology and Region Constraints. 5128-5141 - An Zou
Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management. 5142-5155 - Jinghan Zhang
Allocating One Common ACC-Rich Platform for Many Streaming Applications. 5156-5169 - Jingyu Wang
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators. 5170-5182 - Ayse K. Coskun
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. 5183-5196 - Alexandre Truppel
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. 5197-5210 - Hsin-I Wu
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. 5211-5224 - Iftikhar A. Soomro
Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports. 5225-5237 - Irith Pomeranz
Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load Tests. 5238-5246 - Johan Lidén Eddeland
Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans. 5247-5260 - Irith Pomeranz
LFSR-Based Test Generation for Reduced Fail Data Volume. 5261-5266 - Neil Veira
Searching for Bugs Using Probabilistic Suspect Implications. 5267-5280 - Denny C.-Y. Wu
Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions. 5281-5294 - Gabriel A. G. Andrade
A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs. 5295-5303 - Chia-Chun Lin
A New Necessary Condition for Threshold Function Identification. 5304-5308 - Mikhail M. Pilipko
An Algorithm for the Search of a Low Capacitor Count DAC Switching Scheme for SAR ADCs. 5309-5313
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