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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 22
Volume 22, Number 1, January 2014
- Mustansir Yunus Mukadam, Oscar da Costa Gouveia-Filho, Nicholas Kramer, Xuan Zhang
, Alyssa B. Apsel:
Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers. 1-12 - Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. 13-26 - Henry Park, Chih-Kong Ken Yang:
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. 27-38 - Babak Zamanlooy, Mitra Mirhassani:
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function. 39-48 - Jen-Wei Lee, Szu-Chi Chung
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. 49-61 - Theo Kluter, Philip Brisk
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. 62-75 - Gang He, Dajiang Zhou, Wei Fei, Zhixiang Chen, Jinjia Zhou
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. 76-89 - Jayita Das, Syed M. Alam, Sanjukta Bhanja:
Nano Magnetic STT-Logic Partitioning for Optimum Performance. 90-98 - Farhad Alibeygi Parsan, Waleed K. Al-Assadi, Scott C. Smith:
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. 99-112 - Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. 113-126 - Jing Guo, Liyi Xiao, Zhigang Mao, Qiang Zhao:
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. 127-135 - Kai-Chiang Wu, Diana Marculescu
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment. 136-145 - Ruben Specogna
Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity. 146-154 - Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
Exploring High-Throughput Computing Paradigm for Global Routing. 155-167 - Yazhi Huang, Liang Shi, Jianhua Li, Qing'an Li
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. 168-180 - Jin-Fa Lin:
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through. 181-185 - Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches. 185-190 - Alex Pappachen James
Resistive Threshold Logic. 190-195
Volume 22, Number 2, February 2014
- S. Saqib Khursheed, Kan Shi, Bashir M. Al-Hashimi, Peter R. Wilson, Krishnendu Chakrabarty
Delay Test for Diagnosis of Power Switches. 197-206 - Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. 207-219 - Mohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin
Multivoltage Aware Resistive Open Fault Model. 220-231 - Kashfia Haque, Paul Beckett:
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire. 232-241 - Cédric Killian, Camel Tanougast
Smart Reliable Network-on-Chip. 242-255 - Keheng Huang, Yu Hu, Xiaowei Li:
Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs. 256-269 - Yufu Zhang, Bing Shi, Ankur Srivastava
Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems. 270-279 - Vinicius V. A. Camargo, Ben Kaczer, Gilson I. Wirth
Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits. 280-285 - Alan Kennedy, Xiaojun Wang
Ultra-High Throughput Low-Power Packet Classification. 286-299 - Pradip Kumar Sahu, Tapan Shah, Kanchan Manna, Santanu Chattopadhyay:
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization. 300-312 - Cedric Walravens, Wim Dehaene:
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes. 313-321 - Behzad Zeinali
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs. 322-333 - Rajath Vasudevamurthy
Time-Based All-Digital Technique for Analog Built-in Self-Test. 334-342 - Samaneh Babayan Mashhadi, Reza Lotfi:
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. 343-352 - Shubha Ramakrishnan, Jennifer Hasler:
Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier. 353-361 - Pramod Kumar Meher, Sang Yoon Park:
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. 362-371 - Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. 372-383 - Xuanyao Fong
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. 384-395 - Jianwei Dai, Menglong Guan, Lei Wang:
Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors. 396-407 - Ghaith Tarawneh
Eliminating Synchronization Latency Using Sequenced Latching. 408-419 - Wan-Rone Liou, Mei-Ling Yeh, Ping-Shin Chen, Chun-Chang Tseng, Tang-Yu Huang, Shu-Chia Lin, Cheng-Yu Lin, Chih-Hsiang Sun:
Monolithic Low-EMI CMOS DC-DC Boost Converter for Portable Applications. 420-424 - Taehui Na
Comparative Study of Various Latch-Type Sense Amplifiers. 425-429 - Shubha Ramakrishnan, Arindam Basu
Speech Processing on a Reconfigurable Analog Platform. 430-433 - Cheng-Jyun Li, Tai-Cheng Lee:
2.4-GHz High-Efficiency Adaptive Power. 434-438 - Ahmad Atghiaee
Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems. 438-443 - Cosmin Popa:
Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing. 443-447
Volume 22, Number 3, March 2014
- Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel
Computation on Stochastic Bit Streams Digital Image Processing Case Studies. 449-462 - Yuan-Ho Chen, Jyun-Neng Chen, Tsin-Yuan Chang, Chih-Wen Lu:
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. 463-474 - Min-Sheng Kao, Fanta Chen, Yu-Hao Hsu, Jen-Ming Wu:
20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network. 475-483 - Chin-Yao Chang, Kuen-Jong Lee:
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions. 484-496 - Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim:
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. 497-506 - Yu Liu, Kaijie Wu:
Fault-Duration And-Location Aware CED Technique With Runtime Adaptability. 507-515 - Samah Mohamed Saeed, Ozgur Sinanoglu
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. 516-521 - Server Kasap
Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. 522-536 - Mariangela Genovese, Ettore Napoli:
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video. 537-547 - Ajay N. Bhoj, Niraj K. Jha:
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. 548-561 - Eero Lehtonen
Large-Scale Memristive Associative Memories. 562-574 - Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa:
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. 575-584 - Jong-Kwan Woo, Hyunjoong Lee, Hwi-Cheol Kim, Deog-Kyoon Jeong, Suhwan Kim:
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. 585-592 - Mehdi Saberi
Segmented Architecture for Successive Approximation Analog-to-Digital Converters. 593-606 - Xiang Hu, Peng Du, Shih-Hung Weng, Chung-Kuan Cheng:
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning. 607-620 - Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao:
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. 621-630 - Adrien Le Masle, Wayne Luk:
Mapping Loop Structures Onto Parametrized Hardware Pipelines. 631-640 - Jean-Michel Chabloz, Ahmed Hemani:
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. 641-654 - Xiaodong Liu, Gary K. Yeap, Jun Tao, Xuan Zeng:
Integrated Algorithm for 3-D IC Through-Silicon Via Assignment. 655-666 - Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. 667-674 - Nima Jafarzadeh, Maurizio Palesi, Ahmad Khademzadeh, Ali Afzali-Kusha:
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip. 675-685 - Shunji Nakata
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. 686-690 - Palkesh Jain, Frank Cano, Bapana Pudi, N. V. Arvind:
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs. 691-695 - Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. 696-700
Volume 22, Number 4, April 2014
- Hyun-Woo Lee, Chulwoo Kim:
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. 701-711 - Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. 712-720 - Hong-Ting Lin, Yi-Lin Chuang, Zong-Han Yang, Tsung-Yi Ho
Pulsed-Latch Utilization for Clock-Tree Power Optimization. 721-733 - Mingjing Chen, Alex Orailoglu:
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test. 734-746 - Abhishek A. Sinkar, Hamid Reza Ghasemi, Michael J. Schulte, Ulya R. Karpuzcu, Nam Sung Kim:
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors. 747-758 - Xiaoxiao Zhang, Farid Boussaïd
32 Bit ×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler. 759-770 - Shmuel Wimer, Israel Koren:
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. 771-778 - Irith Pomeranz:
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences. 779-791 - Irith Pomeranz:
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks. 792-802 - Hyoyoung Shin, Youngkyu Park, Gihwa Lee, Jungsik Park, Sungho Kang:
Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress. 803-812 - Davide Sabena, Matteo Sonza Reorda
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. 813-823 - Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang:
Diagnose Failures Caused by Multiple Locations at a Time. 824-837 - Pankaj Golani, Peter A. Beerel:
Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template. 838-849 - Eddie Hung, Steven J. E. Wilton:
Incremental Trace-Buffer Insertion for FPGA Debug. 850-863 - Jason Cong, Bingjun Xiao:
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. 864-877 - Cory E. Merkel, Dhireesha Kudithipudi:
Temperature Sensing RRAM Architecture for 3-D ICs. 878-887 - Syed Ahmed Aamir, Pavel Angelov, J. Jacob Wikner
1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS. 888-898 - Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi:
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. 899-912 - Guoyu Wang, Hongsheng Zhang, Mingying Lu, Chao Zhang, Tao Jiang, Guangyu Guo:
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding. 913-921 - Safar Hatami, Mohamed Helaoui, Fadhel M. Ghannouchi, Massoud Pedram:
Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters. 922-931 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study. 932-937 - Shih-Hung Weng, Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects. 938-942 - Jesús Aguado Ruiz, Antonio J. López-Martín
Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate. 943-947 - Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. 947-951 - Kaiming Nie, Suying Yao, Jiangtao Xu, Jing Gao:
Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator. 951-956
Volume 22, Number 5, May 2014
- Yuhao Wang, Hao Yu, Wei Zhang
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention. 957-970 - Mahmood Khayatzadeh, Yong Lian
Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline. 971-982 - Yansheng Wang, Leibo Liu
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. 983-994 - Mehran Mozaffari Kermani
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2m). 995-1003 - Jonghong Kim, Wonyong Sung:
Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory. 1004-1015 - Xuehui Zhang, Mohammad Tehranipoor:
Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs. 1016-1029 - Shuo Wang, Mohammad Tehranipoor:
Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits. 1030-1041 - Itamar Levi, Alexander Belenky, Alexander Fish
Logical Effort for CMOS-Based Dual Mode Logic Gates. 1042-1053 - Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. 1054-1059 - Min-Woo Lee, Ji-Hwan Yoon, Jongsun Park
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority. 1060-1068 - Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen:
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. 1069-1081 - Xiaowen Wu, Yaoyao Ye, Jiang Xu
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors. 1082-1095 - Ching-Che Chung
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. 1096-1105 - Saket Gupta, Sachin S. Sapatnekar
Variation-Aware Variable Latency Design. 1106-1117 - Takashi Kawamoto, Masato Suzuki, Takayuki Noto:
1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application. 1118-1126 - Behzad Dehlaghi, Sebastian Magierowski, Leonid Belostotski
A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals. 1127-1137 - Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee:
Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization. 1138-1149 - Chun-Yi Lee
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. 1150-1163 - Tien-Yu Lo, Chi-Hsiang Lo:
1-V 365-µW 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS. 1164-1169 - Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis:
Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning. 1170-1174 - Stefania Perri
Area-Delay Efficient Binary Adders in QCA. 1174-1179 - Kejie Huang
Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM. 1179-1182 - Youngjoo Lee
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. 1183-1187 - Daejin Park, Tag Gon Kim:
Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption. 1187-1191 - Jason M. Allred
Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight. 1192-1196 - Junwhan Ahn, Kiyoung Choi:
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology. 1197-1201 - Sumit Jagdish Darak
Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers. 1202-1206
Volume 22, Number 6, June 2014
- Alaa R. Al-Taee, Fei Yuan, Andy Gean Ye, Saman Sadr:
New 2-D Eye-Opening Monitor for Gb/s Serial Links. 1209-1218 - Jinho Han, Hyosup Won, Hyeon-Min Bae:
0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique. 1219-1225 - Byoung-Joo Yoo, Woo-Rham Bae
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit. 1226-1237 - Hao-Chiao Hong
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability. 1238-1247 - Juan Antonio Clemente
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems. 1248-1261 - Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung:
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM. 1262-1269 - Guiqiang Dong, Yangyang Pan, Tong Zhang:
Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance. 1270-1280 - Zhenyu Sun, Xiuyuan Bi, Hai Li
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. 1281-1293 - Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu:
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs. 1294-1307 - Chung-Hsun Huang, Ying-Ting Ma, Wei-Chen Liao:
Design of a Low-Voltage Low-Dropout Regulator. 1308-1313 - Anandaroop Ghosh, Somnath Paul, Jongsun Park
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. 1314-1327 - Rami A. Abdallah, Naresh R. Shanbhag:
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation. 1328-1337 - Inhak Han, Youngsoo Shin:
Simplifying Clock Gating Logic by Matching Factored Forms. 1338-1349 - Chia-Chun Lin, Amlan Chakrabarti
FTQLS: Fault-Tolerant Quantum Logic Synthesis. 1350-1363 - Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures. 1364-1376 - Zhibin Xiao, Bevan M. Baas:
Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks. 1377-1390 - Anh Thien Tran, Bevan M. Baas:
Achieving High-Performance On-Chip Networks With Shared-Buffer Routers. 1391-1403 - Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen:
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function. 1404-1415 - Shan Cao, Zhaolin Li, Fang Wang, Shaojun Wei:
Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling. 1416-1428 - Mauro Olivieri
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. 1429-1440 - Joung-Yeal Kim, Su-Jin Park, Kee-Won Kwon, Bai-Sun Kong, Joo-Sun Choi, Young-Hyun Jun:
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability. 1441-1445 - Yiorgos Sfikas, Yiorgos Tsiatouhas, Said Hamdioui:
Layout-Based Refined NPSF Model for DRAM Characterization and Testing. 1446-1450 - Yuntan Fang, Huawei Li, Xiaowei Li:
Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications. 1450-1455 - Francisco Garcia-Herrero, María José Canet, Javier Valls
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. 1455-1459
Volume 22, Number 7, July 2014
- Yoshiro Riho, Kazuo Nakazato:
Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory. 1461-1469 - Ching-Che Chung
Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID. 1470-1480 - Mohamed Ismail Ali Mohamed, Karim Mohammed, Babak Daneshrad:
Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS. 1481-1490 - Yiqun Wang, Yongpan Liu, Shuangchen Li, Xiao Sheng, Daming Zhang, Mei-Fang Chiang, Baiko Sai, Xiaobo Sharon Hu
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors. 1491-1505 - Salvador Petit
Efficient Register Renaming and Recovery for High-Performance Processors. 1506-1514 - Chao-Tsung Huang, Mehul Tikekar, Anantha P. Chandrakasan:
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding. 1515-1525 - Chao-Lieh Chen, Chien-Hao Lai:
Iterative Linear Interpolation Based on Fuzzy Gradient Model for Low-Cost VLSI Implementation. 1526-1538 - Hayun Chung, Gu-Yeon Wei:
ADC-Based Backplane Receiver Design-Space Exploration. 1539-1547 - Kyoung-Rok Cho, Sang-Jin Lee, Omid Kavehei
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture. 1548-1556 - Salvador Barceló
Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions. 1557-1569 - Irith Pomeranz:
Low-Power Test Generation by Merging of Functional Broadside Test Cubes. 1570-1582 - Amirhossein Alimohammad, Saeed Fouladi Fard:
FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems. 1583-1592 - Elio Consoli, Gaetano Palumbo, Jan M. Rabaey, Massimo Alioto:
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches. 1593-1605 - Sumeet S. Kumar, Arnica Aggarwal, Radhika Sanjeev Jagtap, Amir Zjajo, Rene van Leuken:
System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs. 1606-1619 - Taehui Na
An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM. 1620-1624 - Ioannis Voyiatzis, Costas Efstathiou:
Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells. 1625-1629 - Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. 1630-1634 - Pedro Reviriego
A Method to Extend Orthogonal Latin Square Codes. 1635-1639 - Feng Shi, Xuebin Wu, Zhiyuan Yan:
Improved Analytical Delay Models for RC-Coupled Interconnects. 1639-1644 - Matheus Trevisan Moreira, Fernando Gehm Moraes
Beware the Dynamic C-Element. 1644-1647 - Byeong Yong Kong
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. 1648-1652
Volume 22, Number 8, August 2014
- Sparsh Mittal
MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration. 1653-1665 - Yi-Ping Su, Yean-Kuo Luo, Yi-Chun Chen, Ke-Horng Chen
Current-Mode Synthetic Control Technique for High-Efficiency DC-DC Boost Converters Over a Wide Load Range. 1666-1678 - Jing Chen, Tongquan Wei, Jianlin Liang:
State-Aware Dynamic Frequency Selection Scheme for Energy-Harvesting Real-Time Systems. 1679-1692 - Hui Shao, Xing Li, Chi-Ying Tsui
A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System. 1693-1704 - Haroon Mahmood
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation. 1705-1715 - Sleiman Bou-Sleiman
Dynamic Self-Regulated Charge Pump With Improved Immunity to PVT Variations. 1716-1726 - Chia-Hsiang Chen, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
Design and Evaluation of Confidence-Driven Error-Resilient Systems. 1727-1737 - Dawen Xu, Huawei Li, Amirali Ghofrani, Kwang-Ting Cheng
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. 1738-1749 - Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor
Backend Dielectric Reliability Full Chip Simulator. 1750-1762 - Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson:
Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect. 1763-1776 - Jih-Sheng Shen, Pao-Ann Hsiung:
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip. 1777-1790 - Chih-Hsiang Peng, Bo-Wei Chen, Ta-Wen Kuan, Po-Chuan Lin, Jhing-Fa Wang, Nai-Sheng Shih:
REC-STA: Reconfigurable and Efficient Chip Design With SMO-Based Training Accelerator. 1791-1802 - Shuai Mu, Yangdong Deng, Yubei Chen
Orchestrating Cache Management and Memory Scheduling for GPGPU Applications. 1803-1814 - Mahmoud Zangeneh, Ajay Joshi:
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM. 1815-1828 - Qing'an Li
Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems. 1829-1840 - Cristian Ravariu
Compact NOI Nanodevice Simulation. 1841-1844
Volume 22, Number 9, September 2014
- Sheng Wei, Miodrag Potkonjak:
Self-Consistency and Consistency-Based Detection and Diagnosis of Malicious Circuitry. 1845-1853 - Abhranil Maiti, Patrick Schaumont
The Impact of Aging on a Physical Unclonable Function. 1854-1864 - Hayssam El-Razouk, Arash Reyhani-Masoleh, Guang Gong:
New Implementations of the WG Stream Cipher. 1865-1878 - Wei Wang, Xinming Huang, Niall Emmart, Charles C. Weems:
VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption. 1879-1887 - Li Li, Yinghai Lu, Hai Zhou:
Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling. 1888-1897 - Jatin N. Mistry, James Myers, Bashir M. Al-Hashimi, David Flynn, John Biggs, Geoff V. Merrett
Active Mode Subclock Power Gating. 1898-1908 - Borislav Alexandrov, Owen Sullivan, William J. Song
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices. 1909-1919 - Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC. 1920-1933 - Jintae Kim, Siamak Modjtahedi, Chih-Kong Ken Yang:
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters. 1934-1944 - Craig R. Schlottmann, Jennifer Hasler:
High-Level Modeling of Analog Computational Elements for Signal Processing Applications. 1945-1953 - Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. 1954-1967 - Dong Xiang, Wenjie Sui, Boxue Yin, Kwang-Ting Cheng
Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing. 1968-1979 - Ming-Hong Tsai, Wei-Sheng Ding, Hung-Yi Hsieh, James Chien-Mo Li:
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. 1980-1989 - Davide Rossi
Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators. 1990-2003 - Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
Scalable Effort Hardware Design. 2004-2016 - Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba:
Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability. 2017-2024 - Sangwook Han, David D. Wentzloff:
Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs. 2025-2029 - Cheng-Shang Chang, Jay Cheng, Tien-Ke Huang, Duan-Shin Lee:
Constructions of Memoryless Crosstalk Avoidance Codes Via ${\cal C}$ -Transform. 2030-2033 - Ing-Chao Lin, Kuan-Hui Li, Chia-Hao Lin, Kai-Chiang Wu:
NBTI and Leakage Reduction Using ILP-Based Approach. 2034-2038
Volume 22, Number 10, October 2014
- Sean Keller, David Money Harris, Alain J. Martin:
A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold. 2041-2053 - Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. 2054-2066 - Henry Wong, Vaughn Betz, Jonathan Rose:
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. 2067-2080 - Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore
Power Optimized Transceivers for Future Switched Networks. 2081-2092 - Kyongsu Lee
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS. 2093-2102 - Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou:
PowerRush: An Efficient Simulator for Static Power Grid Analysis. 2103-2116 - Tuck-Boon Chan, Puneet Gupta
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors. 2117-2130 - Aida Todri-Sanial
Globally Constrained Locally Optimized 3-D Power Delivery Networks. 2131-2144 - Krit Athikulwongse, Mongkol Ekpanyapong, Sung Kyu Lim
Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement. 2145-2155 - Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim:
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. 2156-2163 - Behrooz Javid, Payam Heydari:
Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip. 2164-2175 - Mohammad Gholami
Jitter of Delay-Locked Loops Due to PFD. 2176-2180 - Young-sub Yuk, Seungchul Jung, Chul Kim, Hui-Dong Gwon, Sukhwan Choi, Gyu-Hyeong Cho:
PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator. 2181-2191 - Yi-Ping Su, Wei-Chung Chen, Yu-Ping Huang, Yu-Huei Lee, Ke-Horng Chen
Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter. 2192-2205 - Alexei Jolondz, Shlomo Weiss, Amit Golander:
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. 2206-2210 - Bojan Maric, Jaume Abella
Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. 2211-2215 - Chung-Yi Li, Chung-Len Lee, Ming-Hong Hu, Hwai-Pwu Chou:
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor. 2216-2220 - Howard Tang, Zhuochao Sun
A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device. 2220-2224 - Zhe Feng, Naifeng Jing, Lei He:
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. 2225-2228 - Shaoteng Liu, Axel Jantsch
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation. 2229-2233 - C. K. Midhun, Jephy Joy, R. K. Kavitha
High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style. 2233-2237 - Juan Núñez
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. 2238-2242
Volume 22, Number 11, November 2014
- Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng:
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. 2245-2255 - Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. 2256-2267 - Yuan-Ho Chen, Ruei-Yuan Jou, Tsin-Yuan Chang, Chih-Wen Lu:
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy. 2268-2277 - Mozammel H. A. Khan
Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions. 2278-2286 - Michael Lueders, Björn Eversmann, Johannes Gerber, Korbinian Huber, Rüdiger Kuhn, Michael Zwerg, Doris Schmitt-Landsiedel, Ralf Brederlow
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems. 2287-2296 - Sau Siong Chong, Pak Kwong Chan:
A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push-Pull Composite Power Transistor. 2297-2306 - Stephen Brink, Jennifer Hasler, Richard B. Wunderlich:
Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA. 2307-2315 - Yongsheng Xu
A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy. 2316-2325 - Joao Azevedo, Arnaud Virazel
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. 2326-2335 - Wooheon Kang, Hyungjun Cho, Joohwan Lee, Sungho Kang:
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction. 2336-2349 - Kedar Janardan Dhori, Vinay Kumar, Harsh Rawat:
Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory. 2350-2356 - Zhuo Feng:
Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates. 2357-2365 - Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri:
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. 2366-2379 - Hyungsu Sung, Keewon Cho, Kunsang Yoon, Sungho Kang:
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. 2380-2387 - Chun-Chuan Chi, Erik Jan Marinissen
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. 2388-2401 - Yi Wang
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory. 2402-2410 - Chun Zhang, Dian Ma, Changzhi Li
Runtime Self-Calibrated Temperature-Stress Cosensor for 3-D Integrated Circuits. 2411-2417 - Muh-Tian Shiue, Syu-Siang Long, Chin-Kuo Jao, Shih-Kun Lin:
Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas. 2418-2422 - Qing Shang, Yibo Fan, Weiwei Shen, Sha Shen, Xiaoyang Zeng:
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT. 2422-2426 - Irith Pomeranz:
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests. 2427-2431 - Hazem M. Hajj, Wassim El-Hajj
An Algorithm-Centric Energy-Aware Design Methodology. 2431-2435 - Leandro Fiorin, Gianluca Palermo
A Configurable Monitoring Infrastructure for NoC-Based Architectures. 2436-2440 - Karama Mohammed AL-Tamimi
A 6.13 µW and 96 dB CMOS Exponential Generator. 2440-2445
Volume 22, Number 12, December 2014
- Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing. 2449-2461 - Yang Yang, Niraj K. Jha:
FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations. 2462-2475 - Xing Hu, Guihai Yan, Yu Hu, Xiaowei Li:
Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications. 2476-2487 - David Esseni
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. 2488-2498 - Massimo Alioto, David Esseni
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives. 2499-2512 - Hamed Tabkhi, Gunar Schirner
Application-Guided Power Gating Reducing Register File Static Power. 2513-2526 - Inna Vaisband
Digitally Controlled Pulse Width Modulator for On-Chip Power Management. 2527-2534 - Bishnu Prasad Das, Hidetoshi Onodera:
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. 2535-2548 - Zia Abbas
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. 2549-2560 - François Botman, David Bol, Jean-Didier Legat, Kaushik Roy:
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. 2561-2570 - Kedar Karmarkar, Spyros Tragoudas:
Error Correction Encoding for Tightly Coupled On-Chip Buses. 2571-2584 - Gursharan Reehal, Mohammed Ismail:
A Systematic Design Methodology for Low-Power NoCs. 2585-2595 - Amir Reza Baghban Behrouzian, Nasser Masoumi:
Analytical Solutions for Distributed Interconnect Models - Part I: Step Input Response of Finite and Semi-Infinite Lines. 2596-2606 - Ting-Jung Lin
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps. 2607-2620 - Daniel Neil, Shih-Chii Liu:
Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator. 2621-2628 - Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He:
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA. 2629-2634 - Leibo Liu
SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. 2635-2648 - Jun Lin, Zhiyuan Yan:
An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes. 2649-2660 - Hamad Alrimeih, Daler N. Rakhmatov:
Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields. 2661-2674 - Chun-Fu Liao, Jhong-Yu Wang, Yuan-Hao Huang:
A 3.1 Gb/s 8 × 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition. 2675-2688 - Li-Wei Chai, Po-Lin Chiu, Yuan-Hao Huang:
A 2-D Interpolation-Based QRD Processor With Partial Layer Mapping for MIMO-OFDM Systems. 2689-2700 - Ojas A. Bapat, Paul D. Franzon
A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory. 2701-2712 - Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla:
Addressing Partitioning Issues in Parallel Circuit Simulation. 2713-2723 - Scott Koziol, Stephen Brink, Jennifer Hasler:
A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC. 2724-2737 - Jianxin Fang, Sachin S. Sapatnekar
Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits. 2738-2751 - Yanzhi Wang, Xue Lin, Younghyun Kim
Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems. 2752-2765 - Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang:
Utilizing Circuit Structure for Scan Chain Diagnosis. 2766-2778 - Liang Shi, Jianhua Li, Qing'an Li
A Unified Write Buffer Cache Management Scheme for Flash Memory. 2779-2792
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