PicoRV32 - A Size-Optimized RISC-V CPU

SERV - The SErial RISC-V CPU

OpenXuantie - OpenC910 Core

An Open-source FPGA IP Generator

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Verilog I2C interface for FPGA implementation

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

An attempt to recreate the RP2040 PIO in an FPGA

FPGA-based Nintendo Entertainment System Emulator

CoreScore

Chisel components for FPGA projects

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

Raptor end-to-end FPGA Compiler and GUI

A wishbone controlled scope for FPGA's

sliding DFT for FPGA, targetting Lattice ICE40 1k

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

Demo projects for various Kintex FPGA boards

FFT generator using Chisel

The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.

SoftCPU/SoC engine-V

BeagleBone HW, SW, & FPGA Development

Re-coded Xilinx primitives for Verilator use

LunaPnR is a place and router for integrated circuits

Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040

A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented…

OpenFPGA

RTLMeter benchmark suite