Undergraduate student@ University of Tokyo, Dept. of EEIC — Irie-Kadomoto Lab

🔬 Research

• Digital VLSI: fracturable multi-precision floating-point ALU/MAC units for CGRA processing elements (FP32/BF16/FP8) — Best Paper Award @ HEART 2026
• Analog/Mixed-Signal IC Design: front-end (rectifier, LDO, BGR, backscatter) of a mm-scale NFC-powered RISC-V SoC in TSMC 65nm LP

📝 Blog:Note

Verilog, SystemVerilog · Design Compiler · Innovus (PnR) · Cadence Virtuoso/Spectre