🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Open Logic FPGA Standard Library

A huge VHDL library for FPGA and digital ASIC development

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Files used with hackster examples

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

VEXTPROJ - the version control friendly system for creation of Vivado projects

Verilog code for UART communication, including modules for transmitting, receiving, and baud rate generation, along with a testbench for verification.

STM32-style peripheral modules (GPIO, TIM, UART, etc.) and general graphic modules (drivers, algorithms ...) written in Verilog/Chisel/SpinalHDL with APB/AHB/AXI interfaces. Includes a RISC-V SoC e…

Fixed-point math library with VHDL, Python and MATLAB support