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Notes on the Red Pitaya Open Source Instrument
FPGA reference design for the the Swerv EH1 Core
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
A repository of user contributed content for TeXmacs
Sample minimal Vivado project for Parallella FPGA
Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput