OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

An Open-source FPGA IP Generator

A High-performance Timing Analysis Tool for VLSI Systems

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

Verilog Generator of Neural Net Digit Detector for FPGA

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

RePlAce global placement tool

EPFL logic synthesis benchmarks

SystemVerilog synthesis tool

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

Tools for working with circuits as graphs in python

Structural Netlist API (and more) for EDA post synthesis flow development

Plugins for Yosys developed as part of the F4PGA project.

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an…

This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSI…

An automatic clock gating utility

Artificial Netlist Generator

This repository contains the training material for Tapeout Pakistan OpenLane workshop conducted by MERL-UIT.

generic NetList data structure for VLSI

Test suites on Verilog and SystemVerilog standards

IEEE DATC Robust Design Flow 2021.

System Verilog to Verilog

This tool generates a macro_placement.cfg file for use with OpenLANE and OpenFPGA.