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9 results for source starred repositories written in SystemVerilog
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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 1,136 480 Updated May 26, 2025

AMBA AXI VIP

SystemVerilog 426 119 Updated Jun 28, 2024

VeeR EL2 Core

SystemVerilog 302 91 Updated Oct 30, 2025
SystemVerilog 247 59 Updated Dec 22, 2022

Vector processor for RISC-V vector ISA

SystemVerilog 130 26 Updated Oct 19, 2020

UVM AHB VIP

SystemVerilog 87 21 Updated Sep 13, 2025

UVM APB VIP, part of AMBA3&AMBA4 feature supported

SystemVerilog 32 11 Updated Aug 24, 2020

Useful UVM extensions

SystemVerilog 25 6 Updated Jul 10, 2024

Andes Vector Extension support added to riscv-dv

SystemVerilog 17 3 Updated May 29, 2020