Skip to content
View TogashiHan's full-sized avatar

Block or report TogashiHan

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
3 results for source starred repositories written in VHDL
Clear filter

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,898 291 Updated Nov 3, 2025

GPL v3 2D/3D graphics engine in verilog

VHDL 682 145 Updated Aug 31, 2014

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL 143 23 Updated Oct 14, 2025