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written in SystemVerilog
Clear filter
A minimal GPU design in Verilog to learn how GPUs work from the ground up
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Project F brings FPGAs to life with exciting open-source designs you can build on.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
Contains the code examples from The UVM Primer Book sorted by chapters.
Verilog evaluation benchmark for large language model
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.