Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Open source FPGA-based NIC and platform for in-network compute

Verilog AXI components for FPGA implementation

SERV - The SErial RISC-V CPU

Verilog PCI express components

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

HDLBits website practices & solutions

synthesiseable ieee 754 floating point library in verilog

A High-performance Timing Analysis Tool for VLSI Systems

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Example designs showing different ways to use F4PGA toolchains.

An open-source benchmark for generating design RTL with natural language

Structural Netlist API (and more) for EDA post synthesis flow development

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A Standalone Structural Verilog Parser

Re-coded Xilinx primitives for Verilator use

Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.

RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.

A Homework for Computer Architecture at SJTU

A Linux-supported RISC-V SoC for FPGAs, described in Verilog HDL

APBRST: A Pyverilog Based RTL to Specification Translation Tool

University of Utah ECE 6710/5710 Lab Material

A simple RISC-V implementation in verilog

Material for FPGA training for Quest Global