A machine learning accelerator core designed for energy-efficient AI at the edge.

ABC: System for Sequential Logic Synthesis and Formal Verification

Open-source AI acceleration on FPGA: from ONNX to RTL

[DATE'25, ICCAD'25] An embedded FPGA-based LLM accelerator capable of supporting Llama2-7B

Fabric generator and CAD tools.

YouTube Music Desktop App bundled with custom plugins

Niklas Een's ABC/ZZ framework

The HW-CBMC and EBMC Model Checkers for Verilog

A framework to ease parallelization of sequential SAT solvers

Research paper based on or related to ABC.

Duo is an automated tool to formally verify distributed protocols (e.g., Paxos) by inferring inductive invariants.

Public repo for H-Houdini / VeloCT code release for ASPLOS'25

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

AIGER And-Inverter-Graph Library

Certify Model Checking Witnesses in AIGER

FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository

Reads a state transition system and performs property checking

Hardware Model Checker

Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays and uninterpreted functions and their combinations. Its name …

Implementation for the paper: "Implicit Rankings for Verifying Liveness Properties in First-Order Logic"

Yosys Open SYnthesis Suite

C++ logic network library