Lists (32)
3D
15 repositories
AI
28 repositories
Audio
13 repositories
Bash
1 repository
C/C++
14 repositories
ePaper
4 repositories
ESP32
16 repositories
Fonts
35 repositories
FORTH
8 repositories
Fortran
10 repositories
FPGA
14 repositories
Genealogy
4 repositories
Generative
3 repositories
GNOME
4 repositories
HDL
5 repositories
IoT
4 repositories
JS
24 repositories
JSON
3 repositories
KICAD
38 repositories
Oscilloscope
4 repositories
Profiler
5 repositories
RF
20 repositories
RISC-V
36 repositories
Scope
4 repositories
SDR
9 repositories
Space
6 repositories
Synthesis
6 repositories
Ternary
1 repository
UI
25 repositories
Verilog
14 repositories
Wasm
2 repositories
ZIG
9 repositories
Starred repositories
30
stars
written in SystemVerilog
Clear filter
Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A Verilog synthesis flow for Minecraft redstone circuits
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A directory of Western Digital’s RISC-V SweRV Cores
A Linux-capable RISC-V multicore for and by the world
Project F brings FPGAs to life with exciting open-source designs you can build on.
BaseJump STL: A Standard Template Library for SystemVerilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
Test suite designed to check compliance with the SystemVerilog standard.
Public repository for Litefury & Nitefury
tenstorrent / riscv-ocelot
Forked from riscv-boom/riscv-boomOcelot: The Berkeley Out-of-Order Machine With V-EXT support
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …
AXI Adapter(s) for RISC-V Atomic Operations
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definition for VS Code
AXI4-Compatible Verilog Cores, along with some helper modules.
RISC-V assembler/dis-assembler written in SystemVerilog