PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RTL, Cmodel, and testbench for NVDLA

Verilog AXI components for FPGA implementation

SERV - The SErial RISC-V CPU

A small, light weight, RISC CPU soft core

OpenXuantie - OpenC910 Core

Verilog library for ASIC and FPGA designers

The USRP™ Hardware Driver Repository

3-stage RV32IMACZb* processor with debug

synthesiseable ieee 754 floating point library in verilog

A High-performance Timing Analysis Tool for VLSI Systems

Bus bridges and other odds and ends

Repository for basic (and not so basic) Verilog blocks with high re-use potential

OpenSTA engine

VRoom! RISC-V CPU

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

FuseSoC-based SoC for VeeR EH1 and EL2

The USRP™ Hardware Driver FPGA Repository

Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

SystemC/TLM-2.0 Co-simulation framework

Minimax: a Compressed-First, Microcoded RISC-V CPU

Put WebAssembly in your washing machine

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

CoreScore

A collection of demonstration digital filters

FPGA exercise for beginners

Universal Memory Interface (UMI)