OpenTitan: Open source silicon root of trust

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Send video/audio over HDMI on an FPGA

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

This repo is created to include illustrative examples on object oriented design pattern in SV

Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"

Contains source code for sin/cos table verification using UVM

🇯 JSON encoder and decoder in pure SystemVerilog