A minimal GPU design in Verilog to learn how GPUs work from the ground up

Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Send video/audio over HDMI on an FPGA

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Project F brings FPGAs to life with exciting open-source designs you can build on.

The root repo for lowRISC project and FPGA demos.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

training labs and examples

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Source code repo for UVM Tutorial for Candy Lovers

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

FPGA exercise for beginners

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

H265 decoder write in verilog, verified on Xilinx ZYNQ7035

development interface mil-std-1553b for system on chip

SATA sniffing

Verification IP for Watchdog

RIFFA Interface for Intel (Altera) Arria 10 GX & Stratix V GS Development Boards

SRAD GNSS Receiver FPGA design and Firmware