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written in VHDL
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A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…
VUnit is a unit testing framework for VHDL/SystemVerilog
A work-in-progress for what is to be a software-free web server for static content.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
[ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition
Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
Design, Documentation, Schematic, Board, Code files for the FPGA Oscilloscope project using an Altera Cyclone III FPGA.
PYNQ example of using the RFSoC as a QPSK transceiver.
A Bitcoin miner for the Zynq chip utilizing the Zedboard.
Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch
Application software for Scopy MVP: FPGA PS, PL, and microcontroller firmware
achieve softmax in PYNQ with heterogeneous computing.
a Real-time image recognition project with RTL accelerator and ZYNQ Architecture