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A FPGA friendly 32 bit RISC-V CPU implementation
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Functional verification project for the CORE-V family of RISC-V cores.
Self checking RISC-V directed tests
NucleusRV (rv32-imafc) - A 32-bit 5 staged pipelined risc-v core.
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set