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Allows 1-stage (no pipelining) or 2-stage (default) pipeline. Signed-off-by: jerryyin <zhuoryin@amd.com>
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Signed-off-by: jerryyin <zhuoryin@amd.com>
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…ree-org#22673) Adds a `--num-stages` option to the `iree-llvmgpu-prefetch-shared-memory` pass, allowing configuration of pipeline stages. **Options:** - `num-stages=1`: Disable pipelining (no prefetch) - `num-stages=2`: 2-stage pipeline with distance-1 prefetch (default) This PR is mostly trivial changes and aim to get the code base ready to plumb through 3 stage pipelining. --------- Signed-off-by: jerryyin <zhuoryin@amd.com>
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…ree-org#22673) Adds a `--num-stages` option to the `iree-llvmgpu-prefetch-shared-memory` pass, allowing configuration of pipeline stages. **Options:** - `num-stages=1`: Disable pipelining (no prefetch) - `num-stages=2`: 2-stage pipeline with distance-1 prefetch (default) This PR is mostly trivial changes and aim to get the code base ready to plumb through 3 stage pipelining. --------- Signed-off-by: jerryyin <zhuoryin@amd.com>
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Adds a
--num-stagesoption to theiree-llvmgpu-prefetch-shared-memorypass, allowing configuration of pipeline stages.Options:
num-stages=1: Disable pipelining (no prefetch)num-stages=2: 2-stage pipeline with distance-1 prefetch (default)This PR is mostly trivial changes and aim to get the code base ready to plumb through 3 stage pipelining.