Compiler engineer at AMD: MLIR, LLVM, and GPU code generation

_{Triton · TokenSpeed · IREE · rocMLIR · MIOpen · TensorFlow}

I make machine learning models run fast on AMD GPUs. The work spans the stack that gets them there: LLVM intrinsics and MLIR underneath, Triton and IREE in the middle, inference engines and the ROCm libraries above. Eight years at AMD, nearly all of it in code generation and kernel performance, two of them leading the teams that do it.

When a new opportunity comes up, I pick the one that covers a gap in what I understand rather than the one most likely to last. That makes me a poor judge of longevity, and most of what I've worked on has since been deprioritized or folded into something else. It's also why I stepped out of managing rocMLIR and Triton to work on IREE: we had invented a lot of our own machinery in rocMLIR, and I wanted to understand how the upstream MLIR pieces fit together. The range above is the result.

I start from measurement and from reading the generated assembly. The counters show which shapes are losing, the ISA shows why, and together they decide what to work on. I'd rather fix a problem at the level where it belongs, often a layer below where it surfaced, and land it upstream where it keeps working after I've moved on.

_{Or browse every pull request I've opened, and the 660+ I've reviewed.}

Memory movement and data layout

• Triton tt.descriptor_gather/tt.descriptor_scatter for gfx1250 TDM: warp predication, lowering, pipelining, and follow-on hardening.
  _{8 PRs: triton#10019 → … → triton#10564}

  _{[triton#10019](triton-lang/triton#10019) → [triton#10021](triton-lang/triton#10021) → [triton#10157](triton-lang/triton#10157) → [triton#10172](triton-lang/triton#10172) → [triton#10215](triton-lang/triton#10215) → [triton#10230](triton-lang/triton#10230) → [triton#10568](triton-lang/triton#10568) → [triton#10564](triton-lang/triton#10564)}
• Mapped tl.const pointer args onto AMD's constant address space, with upstream pointer-address-space enum and buffer-op format support.
  _{3 PRs: triton#11294 → … → triton#11385}

  _{[triton#11294](triton-lang/triton#11294) → [triton#11379](triton-lang/triton#11379) → [triton#11385](triton-lang/triton#11385)}
• LDS padding and swizzle heuristics at bank-wrap boundaries, unified across async-copy and TDM paths.
  _{3 PRs: triton#9741 → … → triton#9780}

  _{[triton#9741](triton-lang/triton#9741) → [triton#9747](triton-lang/triton#9747) → [triton#9780](triton-lang/triton#9780)}
• Upstream lowering of vector.transfer_read/vector.maskedload to AMDGPU buffer loads with alignment and size guards.
  _{5 PRs: llvm#131803 → … → llvm#146705}

  _{[llvm#131803](llvm/llvm-project#131803) → [llvm#135014](llvm/llvm-project#135014) → [llvm#135982](llvm/llvm-project#135982) → [llvm#138922](llvm/llvm-project#138922) → [llvm#146705](llvm/llvm-project#146705)}
• Pack/unpack folding and layout propagation across LLVM and IREE.
  _{4 PRs: llvm#117340 → … → llvm#146139}

  _{[llvm#117340](llvm/llvm-project#117340) → [iree#19590](iree-org/iree#19590) → [llvm#138332](llvm/llvm-project#138332) → [llvm#146139](llvm/llvm-project#146139)}

Latency hiding and software pipelining

• IREE GPU software pipelining: upstream scf-based prefetching, stage-based prefetcher, then configurable multi-stage pipelines.
  _{8 PRs: iree#22523 → … → iree#22868}

  _{[iree#22523](iree-org/iree#22523) → [iree#22605](iree-org/iree#22605) → [iree#22669](iree-org/iree#22669) → [iree#22673](iree-org/iree#22673) → [iree#22725](iree-org/iree#22725) → [iree#22788](iree-org/iree#22788) → [iree#22818](iree-org/iree#22818) → [iree#22868](iree-org/iree#22868)}
• Multi-buffered, pipelined LDS gathers in IREE on top of upstream MemRef/AMDGPU changes.
  _{8 PRs: llvm#176941 → … → iree#24116}

  _{[llvm#176941](llvm/llvm-project#176941) → [llvm#182364](llvm/llvm-project#182364) → [iree#23354](iree-org/iree#23354) → [iree#23400](iree-org/iree#23400) → [iree#23648](iree-org/iree#23648) → [iree#24114](iree-org/iree#24114) → [iree#24210](iree-org/iree#24210) → [iree#24116](iree-org/iree#24116)}
• Control-flow fission pass isolating transfer ops so prefetching holds across convolution variants. _iree#21018

Tiling, heuristics, and tuning

• Hardware-adaptive GEMM tiling heuristics driven by arithmetic intensity.
  _{6 PRs: iree#21546 → … → iree#21834}

  _{[iree#21546](iree-org/iree#21546) → [iree#21638](iree-org/iree#21638) → [iree#21691](iree-org/iree#21691) → [iree#21803](iree-org/iree#21803) → [iree#21826](iree-org/iree#21826) → [iree#21834](iree-org/iree#21834)}
• TokenSpeed MXFP4 MoE decode on gfx1250: base path, expert-load tile sizing, warp-distributed gather/scatter indices.
  _{6 PRs: tokenspeed#1100 → … → tokenspeed#1622}

  _{[tokenspeed#1100](lightseekorg/tokenspeed#1100) → [tokenspeed#1194](lightseekorg/tokenspeed#1194) → [tokenspeed#1455](lightseekorg/tokenspeed#1455) → [tokenspeed#1503](lightseekorg/tokenspeed#1503) → [tokenspeed#1578](lightseekorg/tokenspeed#1578) → [tokenspeed#1622](lightseekorg/tokenspeed#1622)}
• Unified rocMLIR's blockwise and matrix-core GEMM paths behind transform-map-driven vectorization, extended to gridwise GEMM for convolution.
  _{5 PRs: rocMLIR#699 → … → rocMLIR#829}

  _{[rocMLIR#699](ROCm/rocMLIR#699) → [rocMLIR#711](ROCm/rocMLIR#711) → [rocMLIR#754](ROCm/rocMLIR#754) → [rocMLIR#768](ROCm/rocMLIR#768) → [rocMLIR#829](ROCm/rocMLIR#829)}

Operators, precision, and library integration

• int8 convolution in rocMLIR via implicit GEMM: lowering, kernels, tuning, CI.
  _{9 PRs: rocMLIR#485 → … → rocMLIR#618}

  _{[rocMLIR#485](ROCm/rocMLIR#485) → [rocMLIR#494](ROCm/rocMLIR#494) → [rocMLIR#505](ROCm/rocMLIR#505) → [rocMLIR#508](ROCm/rocMLIR#508) → [rocMLIR#539](ROCm/rocMLIR#539) → [rocMLIR#568](ROCm/rocMLIR#568) → [rocMLIR#601](ROCm/rocMLIR#601) → [rocMLIR#611](ROCm/rocMLIR#611) → [rocMLIR#618](ROCm/rocMLIR#618)}
• Reduction-xdlops tuning-space removal and GEMM perf refactors.
  _{7 PRs: rocMLIR#689 → … → rocMLIR#754}

  _{[rocMLIR#689](ROCm/rocMLIR#689) → [rocMLIR#699](ROCm/rocMLIR#699) → [rocMLIR#711](ROCm/rocMLIR#711) → [rocMLIR#724](ROCm/rocMLIR#724) → [rocMLIR#727](ROCm/rocMLIR#727) → [rocMLIR#734](ROCm/rocMLIR#734) → [rocMLIR#754](ROCm/rocMLIR#754)}
• Quantization ops and MIGraphX int8 quantization end-to-end.
  _{10 PRs: rocMLIR#969 → … → rocMLIR#1105}

  _{[rocMLIR#969](ROCm/rocMLIR#969) → [rocMLIR#990](ROCm/rocMLIR#990) → [rocMLIR#999](ROCm/rocMLIR#999) → [rocMLIR#1005](ROCm/rocMLIR#1005) → [rocMLIR#1024](ROCm/rocMLIR#1024) → [rocMLIR#1031](ROCm/rocMLIR#1031) → [rocMLIR#1034](ROCm/rocMLIR#1034) → [rocMLIR#1078](ROCm/rocMLIR#1078) → [rocMLIR#1089](ROCm/rocMLIR#1089) → [rocMLIR#1105](ROCm/rocMLIR#1105)}
• 52 pull requests into upstream TensorFlow (kernels, XLA, StreamExecutor, and the Python front end) and 83 more into AMD's ROCm fork, covering 3D convolution, RNN kernel gaps, layer normalization, dropout, and batched GEMM.

_{Repositories · Gists · Pull requests}