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Financial data platform for analysts, quants and AI agents.

Python 55,789 5,419 Updated Dec 23, 2025
Python 2,495 725 Updated Aug 6, 2025

🦄🦄🦄AI赋能股票分析:AI加持的股票分析/选股工具。股票行情获取,AI热点资讯分析,AI资金/财务分析,涨跌报警推送。支持A股,港股,美股。支持市场整体/个股情绪分析,AI辅助选股等。数据全部保留在本地。支持DeepSeek,OpenAI, Ollama,LMStudio,AnythingLLM,硅基流动,火山方舟,阿里云百炼等平台或模型。

Go 3,499 566 Updated Dec 19, 2025

基于Python的开源量化交易平台开发框架

Python 34,877 10,544 Updated Dec 24, 2025

stock股票.获取股票数据,计算股票指标,筹码分布,识别股票形态,综合选股,选股策略,股票验证回测,股票自动交易,支持PC及移动设备。

Python 10,976 2,217 Updated Aug 28, 2025

stock,股票系统。使用python进行开发。

Python 7,544 2,348 Updated Sep 30, 2025

OpenStock is an open-source alternative to expensive market platforms. Track real-time prices, set personalized alerts, and explore detailed company insights — built openly, for everyone, forever f…

TypeScript 6,520 775 Updated Dec 12, 2025

股票看盘小工具

Python 2 Updated Jan 2, 2023

【摸鱼看盘】一个轻量极简的 VS Code 股票实时查看插件,让您在编码的同时轻松掌握股市动态。

JavaScript 12 2 Updated Dec 17, 2025

CoralNPU behavior simulator based on MPACT-Sim

C++ 16 3 Updated Dec 23, 2025

AXI interface modules for Cocotb

Python 303 98 Updated Sep 30, 2025

🚀🚀 「大模型」2小时完全从0训练26M的小参数GPT!🌏 Train a 26M-parameter GPT from scratch in just 2h!

Python 36,095 4,262 Updated Dec 24, 2025
C++ 120 56 Updated Dec 25, 2025

猫抓 浏览器资源嗅探扩展 / cat-catch Browser Resource Sniffing Extension

JavaScript 17,353 1,495 Updated Dec 20, 2025

NYU Processor Design Team's interpretation of ARM's AMBA specifications.

SystemVerilog 2 6 Updated Sep 3, 2024

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.

C++ 4 12 Updated Sep 3, 2024

Common SystemVerilog RTL modules for RgGen

SystemVerilog 15 3 Updated Dec 23, 2025

Setup scripts and files needed to compile CoreMark on RISC-V

C 72 32 Updated Jul 19, 2024

Financial Technology with SoC-NTM verified with UVM/OSVVM/FV

SystemVerilog 8 1 Updated Dec 17, 2025

The SoC Design for Time-Sensitive Networking (TSN)

Verilog 22 3 Updated Dec 5, 2025

Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).

Verilog 60 23 Updated Dec 15, 2025

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog 335 74 Updated Dec 11, 2024

An open silicon CHERIoT Ibex microcontroller chip

C 17 4 Updated May 23, 2025

A demo system for Ibex including debug support and some peripherals

C 85 68 Updated Nov 4, 2025

Bus bridges and other odds and ends

Verilog 612 118 Updated Apr 14, 2025

10Gb Ethernet Switch

C 244 30 Updated Oct 16, 2025

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port i…

C++ 50 5 Updated Dec 25, 2025

Cycle accurate C++ model of CAN bus according to ISO11898-2015 and compliance tests according to ISO16845-2016.

C++ 5 Updated Dec 20, 2025

This is a mirror repository for official CTU CAN FD repository:

VHDL 34 13 Updated Dec 24, 2025

List of awesome semiconductor startups

Python 689 117 Updated Jul 29, 2025
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