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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
A Linux-capable RISC-V multicore for and by the world
BaseJump STL: A Standard Template Library for SystemVerilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Verification IP for APB protocol
System on Chip verified with UVM/OSVVM/FV
Verification IP for AMBA APB Protocol
A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
Mirror of william_william/uvm-mcdf on Gitee
svlib from http://www.verilab.com/resources/svlib/
AXI4 with a FIFO integrated with VIP
Andes Vector Extension support added to riscv-dv