A minimal GPU design in Verilog to learn how GPUs work from the ground up

Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

A directory of Western Digital’s RISC-V SweRV Cores

A Linux-capable RISC-V multicore for and by the world

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

BaseJump STL: A Standard Template Library for SystemVerilog

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

AMBA AXI VIP

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

RISC-V CPU Core

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

An AXI4 crossbar implementation in SystemVerilog

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

VIP for AXI Protocol

AHB3-Lite Interconnect

AXI总线连接器

UVM AHB VIP

Verification IP for APB protocol

opensource NPU for LLM inference (this run gpt2)

This is for uvm_tb_gen

A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS

System on Chip verified with UVM/OSVVM/FV