PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Verilog PCI express components

A small, light weight, RISC CPU soft core

OpenXuantie - OpenC910 Core

An open source GPU based off of the AMD Southern Islands ISA.

RISC-V XV6/Linux SoC, marchID: 0x2b

Various HDL (Verilog) IP Cores

Bus bridges and other odds and ends

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog UART

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

AMBA bus lecture material

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

This is a repository containing solutions to the problem statements given in HDL Bits website.

FuseSoC-based SoC for VeeR EH1 and EL2

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

uvm AXI BFM(bus functional model)

Small-scale Tensor Processing Unit built on an FPGA

OpenXuantie - OpenE902 Core

hardware design of universal NPU(CNN accelerator) for various convolution neural network