GPGPU supporting RISCV-V, developed with verilog HDL

AXI DMA 32 / 64 bits

包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;

AXI Interface Nand Flash Controller (Sync mode)

DDR2 memory controller written in Verilog

OpenSPARC-based SoC

XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.

用Altera FPGA芯片自制CPU

学习AXI接口，以及xilinx DDR3 IP使用

Must-have verilog systemverilog modules

SoC Based on ARM Cortex-M3

QSPI for SoC

12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm

this repository is a project about iic master, created by gyj in second half of 2017

AXI DMA Check: A utility to measure DMA speeds in simulation

Verilog Model for W25Q128JVxIM Serial Flash Memory

Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU

This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.

RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核

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实现带有BD（Buffer Description缓存描述符）的四通道DMA控制器设计，每个通道包括配置寄存器模块，源端控制模 块，缓存模块和目的端控制模块

AZ Processor SoC, reference book : 《CPU自制入门》

"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"