RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

The Xyce™ Parallel Electronic Simulator

gpt-oss-120b and gpt-oss-20b are two open-weight language models by OpenAI

北京大学计算机基础能力手册

Code for "Neuromorphic Dreaming": Efficient RL using SNNs and MBRL on the DYNAP-SE neuromorphic chip.

Event datasets and transforms.

The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully implements the RISC-V specification.

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

An open-source long-horizon SuperAgent harness that researches, codes, and creates. With the help of sandboxes, memories, tools, skill, subagents and message gateway, it handles different levels of…